7024S55GB IDT, 7024S55GB Datasheet
7024S55GB
Manufacturer Part Number
7024S55GB
Description
SRAM
Manufacturer
IDT
Series
IDT7024S, IDT7024Lr
Type
Asyncronous Static RAMr
Datasheet
1.7024S55GB.pdf
(22 pages)
Specifications of 7024S55GB
Memory Size
64 kbit
Organization
4 K x 16
Access Time
55 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
250 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Package / Case
PGA-84
Memory Type
CMOS
Part # Aliases
IDT7024S55GB
Features
Functional Block Diagram
©2008 Integrated Device Technology, Inc.
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7024S
– IDT7024L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
I/O
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
I/O
8L
0L
BUSY
-I/O
SEM
-I/O
R/W
A
INT
UB
CE
OE
LB
A
11L
15L
0L
7L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
12
Control
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts availble, see ordering information
Control
I/O
12
Address
Decoder
CE
OE
R/W
R
R
R
OCTOBER 2008
IDT7024S/L
2740 drw 01
R/W
UB
LB
CE
OE
I/O
I/O
BUSY
A
A
SEM
INT
11R
0R
R
8R
0R
R
R
R
R
R
(2)
R
-I/O
-I/O
R
(1,2)
15R
7R
DSC 2740/13
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