MAX13444EASA/V+ Maxim Integrated, MAX13444EASA/V+ Datasheet - Page 14

• Manufacturer Part Number: MAX13444EASA/V+
• Description: RS-485 Interface IC +/-80V Fault Protected RS-485 Half-Duplex Transceiver with Foldback Current Limit
• Manufacturer: Maxim Integrated

Specifications of MAX13444EASA/V+

• Data Rate: 10 Mbps
• Operating Supply Voltage: 5 V
• Supply Current: 30 mA
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Function: Transceiver
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 1
• Number Of Receivers: 1
• Propagation Delay Time Ns: 50 ns
• Shutdown: Yes

Inserting circuit boards into a hot, or powered, back-
plane may cause voltage transients on DE, RE, and
receiver inputs A and B that can lead to data errors. For
example, upon initial circuit board insertion, the proces-
sor undergoes a power-up sequence. During this period,
the high-impedance state of the output drivers makes
them unable to drive the MAX13442E/MAX13443E/
MAX13444E enable inputs to a defined logic level.
Meanwhile, leakage currents of up to 10µA from the
high-impedance output, or capacitively coupled noise
from V
incorrect logic state. To prevent such a condition from
occurring, the MAX13442E/MAX13443E/MAX13444E
feature hot-swap input circuitry on DE, and RE to guard
against unwanted driver activation during hot-swap sit-
uations. The MAX13444E has hot-swap input circuitry
only on RE. When V
pullup for RE) circuit holds DE low for at least 10µs, and
until the current into DE exceeds 200µA. After the initial
power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
±15kV ESD-Protected, ±80V Fault-Protected,
Fail-Safe RS-485/J1708 Transceivers
Figure 9a. Human Body ESD Test Model
Figure 9b. Human Body Model Current Waveform
14
AMPERES
VOLTAGE
SOURCE
______________________________________________________________________________________
HIGH-
DC
CC
I
P
36.8%
100%
90%
10%
or GND, could cause an input to drift to an
CHARGE-CURRENT-
0
LIMIT RESISTOR
0
1MΩ
t
RL
R
C
100pF
C s
CC
rises, an internal pulldown (or
CURRENT WAVEFORM
STORAGE
CAPACITOR
TIME
1.5kΩ
RESISTANCE
DISCHARGE
R
D
t
DL
Hot-Swap Capability
I r
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Hot-Swap Inputs
DEVICE
UNDER
TEST
At the driver-enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 10). When V
zero, an internal 15µs timer turns on M2 and sets the
SR latch, which also turns on M1. Transistors M2, a
2mA current sink, and M1, a 100µA current sink, pull
DE to GND through a 5.6kΩ resistor. M2 pulls DE to the
disabled state against an external parasitic capaci-
tance up to 100pF that may drive DE high. After 15µs,
the timer deactivates M2 while M1 remains on, holding
DE low against three-state leakage currents that may
drive DE high. M1 remains on until an external current
source overcomes the required input current. At this
time, the SR latch resets M1 and turns off. When M1
turns off, DE reverts to a standard, high-impedance
CMOS input. Whenever V
is reset.
A complementary circuit for RE uses two PMOS
devices to pull RE to V
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
(HOT SWAP)
DE
TIMER
V
CC
5.6kΩ
TIMER
M1
CC
100μA
15μs
.
CC
2mA
Hot-Swap Input Circuitry
drops below 1V, the input
M2
CC
ramps from