71V3558S166PFG

Manufacturer Part Number71V3558S166PFG
DescriptionSRAM
ManufacturerIDT
71V3558S166PFG datasheet
 


Specifications of 71V3558S166PFG

Product CategorySRAMRohsyes
Part # AliasesIDT71V3558S166PFG  
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Features
◆ ◆ ◆ ◆ ◆
128K x 36, 256K x 18 memory configurations
◆ ◆ ◆ ◆ ◆
Supports high performance system speed - 200 MHz (x18)
(3.2 ns Clock-to-Data Access)
◆ ◆ ◆ ◆ ◆
Supports high performance system speed - 166 MHz (x36)
(3.5 ns Clock-to-Data Access)
◆ ◆ ◆ ◆ ◆
TM
ZBT
Feature - No dead cycles between write and read
cycles
◆ ◆ ◆ ◆ ◆
Internally synchronized output buffer enable eliminates the
need to control OE
◆ ◆ ◆ ◆ ◆
Single R/W (READ/WRITE) control pin
◆ ◆ ◆ ◆ ◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆ ◆ ◆ ◆ ◆
4-word burst capability (interleaved or linear)
◆ ◆ ◆ ◆ ◆
Individual byte write (BW
- BW
) control (May tie active)
1
4
◆ ◆ ◆ ◆ ◆
Three chip enables for simple depth expansion
◆ ◆ ◆ ◆ ◆
3.3V power supply (±5%), 3.3V I/O Supply (V
◆ ◆ ◆ ◆ ◆
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆ ◆ ◆ ◆ ◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Pin Description Summary
A
-A
Address Inputs
0
17
Chip Enables
, CE
, CE
CE
1
2
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
, BW
, BW
, BW
BW
1
2
3
4
CLK
Clock
ADV/LD
Advance b urst address / Load new address
Linear / Interleaved Burst Order
LBO
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
JTAG Reset (Optional)
TRST
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be
it read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
DDQ)
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
1
IDT71V3556S/XS
IDT71V3558S/XS
IDT71V3556SA/XSA
IDT71V3558SA/XSA
, or
TM
, CE
, CE
) that allow the
1
2
2
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5281 tbl 01
OCTOBER 2010
DSC-5281/11

71V3558S166PFG Summary of contents

  • Page 1

    ... Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/ suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values ...

  • Page 2

    ... CE and CE 1 This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with N/A respect to the rising edge of CLK. Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and N/A triggered by the rising edge of CLK ...

  • Page 3

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram Commercial and Industrial Temperature Ranges 3 6.42 ...

  • Page 4

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram Recommended DC Operating Conditions Symbol Parameter Min. V Core Supply Voltage 3.135 DD V I/O Supply Voltage 3.135 DDQ V Supply Voltage ...

  • Page 5

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage Grade Temperature V (1) SS Commercial 0°C to +70°C 0V Industrial -40°C to +85°C 0V NOTES the "instant on" case temperature. ...

  • Page 6

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Pin Configuration - 256K x 18 100 DDQ I ...

  • Page 7

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 119 BGA DDQ I I DDQ I I DDQ K I I/O 25 ...

  • Page 8

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 165 fBGA (2) CE1 I DDQ D I/O I DDQ E I/O I ...

  • Page 9

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Synchronous Truth Table CEN (5) R/W Chip ADV/LD Enable L L Select Select Deselect ...

  • Page 10

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Interleaved Burst Sequence Table (LBO=V First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. ...

  • Page 11

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles Cycle Address R/W ADV ...

  • Page 12

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation Cycle Address R/W ADV ...

  • Page 13

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Read Operation with Clock Enable Used Cycle Address R/W ADV n+6 A ...

  • Page 14

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Read Operation with CHIP Enable Used Cycle Address R/W ADV ...

  • Page 15

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LBO, JTAG and ZZ Input Leakage Current ...

  • Page 16

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs AC Electrical Characteristics (V = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock Frequence t F (2) Clock High Pulse Width ...

  • Page 17

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Read Cycle Commercial and Industrial Temperature Ranges (1,2,3, ...

  • Page 18

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Write Cycles Commercial and Industrial Temperature Ranges (1,2,3,4,5) 18 6.42 ...

  • Page 19

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Combined Read and Write Cycles Commercial and Industrial Temperature Ranges (1,2, ...

  • Page 20

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CEN Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 20 6.42 ...

  • Page 21

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CS Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 21 6.42 , ...

  • Page 22

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. ...

  • Page 23

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Available JTAG Instructions ...

  • Page 24

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline Commercial and Industrial Temperature Ranges 24 6.42 ...

  • Page 25

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 119 Ball Grid Array (BGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 25 6.42 ...

  • Page 26

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 26 6.42 ...

  • Page 27

    ... IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation OE DATA OUT NOTE read operation is assumed progress. Ordering Information Commercial and Industrial Temperature Ranges ...

  • Page 28

    ... Added X generation die step to data sheet. Remove 200MHz on 128K x 36 configuration. Removed IDT from the ordering information for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 28 6.42 Commercial and Industrial Temperature Ranges at 133MHz and 100MHz for Tech Support: sramhelp@idt.com ...