CAT1023WI-25-G ON Semiconductor, CAT1023WI-25-G Datasheet - Page 7

• Manufacturer Part Number: CAT1023WI-25-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1023WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

Reset Controller Description
correct system operation during brownout and power
up/down conditions. They are configured with open drain
RESET outputs.
V
outputs for approximately 200 ms (t
V
to drive the reset outputs. At this point the reset outputs will
be pulled up or down by their respective pull up/down
resistors.
when V
so long as V
to ignore the fast negative going V
(glitches).
Manual Reset Operation
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
input. Driving the MR input low by connecting a pushbutton
(normally open) from MR pin to GND will generate a reset
condition. The input has an internal pull up resistor.
Timeout period after MR input has gone high.
a reset pulse. No external debouncing circuits are required.
Manual reset operation using MR input is shown in Figure 2.
CC
TH
The CAT1021/22/23 precision RESET controllers ensure
During power−up, the RESET outputs remain active until
During power−down, the RESET outputs will be active
Reset output timing is shown in Figure 1.
The RESET pin can operate as reset output and manual
When RESET I/O is driven to the active state, the 200 ms
The CAT1021/22/23 also have a separate manual reset
Reset remains asserted while MR is low and for the Reset
Glitches shorter than 100 ns on MR input will not generate
. After the t
reaches the V
CC
falls below V
CC
is >1.0 V (V
PURST
TH
threshold and will continue driving the
timeout interval, the device will cease
TH
. The RESET output will be valid
RVALID
). The device is designed
PURST
CC
transient pulses
) after reaching
DEVICE OPERATON
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7
Hardware Data Protection
solve many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which is
assumed to hold correct data.
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are active,
in progress communications to the EEPROM are aborted
and no new communications are allowed. In this condition
an internal write cycle to the memory can not be started, but
an in progress internal nonvolatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before V
of 2V.
Input which when tied to V
operations to the device.
Watchdog Timer
for
CAT1021/22/23 devices will provide a reset signal after a
time−out interval of 1.6 seconds for a lack of activity. The
CAT1023 is designed with the Watchdog timer feature on
the WDI pin. The CAT1021 and CAT1022 monitor the SDA
line. If WDI or SDA does not toggle within a 1.6 second
interval, the reset condition will be generated on the reset
outputs. The watchdog timer is cleared by any transition on
a monitored line.
not count and will stay cleared.
The CAT1021/22/23 supervisors have been designed to
Whenever the device is in a Reset condition, the
In addition, the CAT1021 includes a Write Protection
The Watchdog Timer provides an independent protection
As long as reset signal is asserted, the watchdog timer will
microcontrollers.
During
CC
reaches the minimum value
CC
will disable any write
a
system
failure,