CAT1022WI-25-G ON Semiconductor, CAT1022WI-25-G Datasheet - Page 10

• Manufacturer Part Number: CAT1022WI-25-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1022WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
a START condition and its slave address. If the device has
been selected along with a write operation, it responds with
an acknowledge after receiving each 8−bit byte.
Byte Write
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the device.
After receiving another acknowledge from the Slave, the
After a successful data transfer, each receiving device is
All devices respond with an acknowledge after receiving
In the Byte Write mode, the Master device sends the
FROM TRANSMITTER
FROM RECEIVER
SD
SCL
DATA OUTPUT
DATA OUTPUT
A
Default Configuration
SCL FROM
MASTER
START BIT
STA
RT
Figure 6. Acknowledge Timing
Figure 7. Slave Address Bits
Figure 5. Start/Stop Timing
WRITE OPERATIONS
1
ACKNOWLEDGE
http://onsemi.com
1
0
10
1
data, releases the SDA line and monitors the line for an
acknowledge. Once it receives this acknowledge, the device
will continue to transmit data. If no acknowledge is sent by
the Master, the device terminates data transmission and
waits for a STOP condition.
Master device transmits the data to be written into the
addressed memory location. The device acknowledges once
more and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle to
non−volatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
When a device begins a READ mode it transmits 8 bits of
0
0
0
8
STOP BIT
ACKNOWLEDGE
0
R/W
9