7024S55JI IDT, 7024S55JI Datasheet - Page 17

• Manufacturer Part Number: 7024S55JI
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55JI

• Part # Aliases: IDT7024S55JI

Truth Table IV —
Address BUSY Arbritration
NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2. There are eight semaphore flags written to via I/O
3. CE = V
Functional Description
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7024 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE = V
When a port is enabled, access to the entire memory array is permitted.
Interrupts
Truth Table V — Example of Semaphore Procurement Sequence
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
X
H
X
L
push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.
and enable inputs of this port. If t
when BUSY
The IDT7024 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
L
CE
IH
X
X
H
L
, SEM = V
R
Inputs
L
R
and BUSY
outputs are driving LOW regardless of actual logic level on the pin.
Functions
NO MATCH
A
A
MATCH
MATCH
MATCH
0R
0L
IL
, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.
-A
-A
R
11L
11R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY
APS
BUSY
is not met, either BUSY
(2)
H
H
H
L
Outputs
(1)
D
BUSY
0
0
- D
(2)
and read from all the I/O's. These eight semaphores are addressed by A0-A2.
H
H
H
L
1
0
0
1
1
0
1
1
1
0
1
15
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
R
(1)
Left
L
or BUSY
Write Inhibit
Function
Normal
Normal
Normal
D
0
R
2740 tbl 17
- D
IH
= LOW will result. BUSY
15
).
1
1
1
1
1
1
1
1
0
0
0
6.42
(3)
17
Right
or message center) is assigned to each port. The left port interrupt flag
(INT
(HEX), where a write is defined as the CE = R/W = V
III. The left port clears the interrupt by access address location FFE access
when CE
interrupt flag (INT
FFF (HEX) and to clear the interrupt flag (INT
the memory location FFF. The message (16 bits) at FFE or FFF is user-
defined, since it is an addressable SRAM location. If the interrupt function
L
) is asserted when the right port writes to memory location FFE
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Military, Industrial and Commercial Temperature Ranges
R
= OE
L
and BUSY
R
R =
) is asserted when the left port writes to memory location
V
IL,
R/W
R
outputs cannot be LOW simultaneously.
is a "don't care". Likewise, the right port
Status
R
), the right port must access
X
outputs on the IDT7024 are
IL
per the Truth Table
(1,2,3)
2740 tbl 18