MAX1785EUU+T Maxim Integrated, MAX1785EUU+T Datasheet - Page 13

• Manufacturer Part Number: MAX1785EUU+T
• Description: Battery Management Smart Battery-Pack Controller
• Manufacturer: Maxim Integrated
• Series: MAX1785r

Figure 11. Typical Offset Termination
The circuit of Figure 11 shows a typical offset termina-
tion used to guarantee a greater than 200mV offset
when a line is not driven (the 50pF represents the mini-
mum parasitic capacitance that would exist in a typical
application). During a hot-swap event when the driver
is connected to the line and is powered up, the driver
must not cause the differential signal to drop below
200mV. Figures 12, 13, and 14 show the results of the
MAX3060E during power-up for three different V
ramp rates (0.1V/µs, 1V/µs, and 10V/µs). The photos
show the V
side of the 100Ω termination, as well as the differential
signal across the termination.
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. The
MAX3060E family’s receiver inputs/driver outputs (A, B)
have extra protection against static electricity found in
normal operation. Maxim’s engineers developed state-
of-the-art structures to protect these pins against
±15kV ESD without damage. After an ESD event, the
devices continue working without latchup.
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
• ±15kV using the Human Body Model
• ±7kV using the Contact Discharge method specified
• ±7kV using the Air-Gap Discharge method specified
±15kV ESD-Protected, Fail-Safe, 20Mbps, Slew-Rate-
in IEC 1000-4-2 (formerly IEC 801-2)
in IEC 1000-4-2 (formerly IEC 801-2)
Limited RS-485/RS-422 Transceivers in a SOT
CC
V
CC
OR GND
ramp, the single-ended signal on each
DI
______________________________________________________________________________________
V
CC
A
B
±15kV ESD Protection
5.0V
Hot-Swap Line Transient
1kΩ
0.1kΩ
1kΩ
50pF
CC
Figure 12. Differential Power-Up Glitch (0.1V/µs)
Figure 13. Differential Power-Up Glitch (1V/µs)
Figure 14. Differential Power-Up Glitch (10V/µs)
A - B
A - B
A - B
V
V
V
CC
CC
CC
A
B
A
A
B
B
200ns/div
40μs/div
2μs/div
5V
0
200mV/div
200mV/div
5V
0
50mV/div
238mV
20mV/div
5V
0
20mV/div
20mV/div
50mV/div
238mV
20mV/div
238mV
20mV/div
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