CAT1021ZI-25-G ON Semiconductor, CAT1021ZI-25-G Datasheet - Page 9

• Manufacturer Part Number: CAT1021ZI-25-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1021ZI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MSOP-8
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

EEPROM that supports the I
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I
follows:
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
2
C Bus Protocol
The CAT1021/22/23 feature a 2−kbit embedded serial
The features of the I
The Master begins a transmission by sending a START
The last bit of the slave address specifies whether a Read
1. Data transfer may be initiated only when the bus is
not busy.
SCL
SDA
SDA OUT
SDA IN
SCL
2
t SU:STA
C bus protocol are defined as
2
C Bus data transmission
8TH BIT
BYTE n
t F
EMBEDDED EEPROM OPERATON
t HD:STA
t LOW
ACK
Figure 4. Write Cycle Timing
DEVICE ADDRESSING
t AA
Figure 3. Bus Timing
t HD:DAT
t HIGH
http://onsemi.com
STOP
CONDITION
t LOW
9
Start Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1021/22/23 monitor the SDA
and SCL lines and will not respond until this condition is
met.
Stop Condition
determines the STOP condition. All operations must end
with a STOP condition.
address byte, the CAT1021/22/23 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1021/22/23 then perform a Read or Write operation
depending on the R/W bit.
t DH
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
After the Master sends a START condition and the slave
t SU:DAT
2. During a data transfer, the data line must remain
t R
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
t WR
START
CONDITION
t SU:STO
t BUF
ADDRESS