70V05L15PF IDT, 70V05L15PF Datasheet
70V05L15PF
Specifications of 70V05L15PF
Related parts for 70V05L15PF
70V05L15PF Summary of contents
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... IDT70V05S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V05L Active: 380mW (typ.) Standby: 660 µ W (typ.) IDT70V05 easily expands data bus width to 16 bits or more ◆ ◆ ◆ ◆ ◆ using the Master/Slave select when cascading more than Functional Block Diagram OE L ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Description The IDT70V05 is a high-speed Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM combination MASTER/SLAVE Dual-Port SRAM for 16-bit- or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...
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... This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking. (con't BUSY M INT BUSY IDT70V05G (4) G68-1 68-Pin PGA (5) Top View I I/O I/O ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control ) NOTE — A ≠ A — 12L 0R 12R Truth Table II: Semaphore Read/Write Control ) ...
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... NOTES > -1.5V for pulse width less than 10ns TERM ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Test Conditions ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no BDD relation to valid output data ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage ...
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... Timing depends on which enable signal is asserted last, CE, or R/W. 7. Timing depends on which enable signal is de-asserted first, CE LOW during R/W controlled write cycle, the write pulse width must be the larger of t bus for the required HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE for the duration of the above timing (both write and read cycle “DATA VALID” ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read with BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES must be met for both BUSY input (slave) and output (master BUSY is asserted on port “B” Blocking R/W “B” only for the slave version. ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05. 2. There are eight semaphore flags written to via I SEM = V to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table (1) ...
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... IDT70V05S/L High-Speed 3. Dual-Port Static RAM BUSY (L) Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs. Functional Description The IDT70V05 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory ...
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... The eight semaphore flags reside within the IDT70V05 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts ...
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... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT70V05’s Dual-Port SRAM. Say the SRAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. ...
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... Page 22 Removed "IDT" from orderable part number 06/14/12: Page 11 Corrected footnote 9 from V Page 22 Added T& R indicator to ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc Process/ Temperature Range ...