CAT1021ZI-45-G ON Semiconductor, CAT1021ZI-45-G Datasheet - Page 11

• Manufacturer Part Number: CAT1021ZI-45-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1021ZI-45-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MSOP-8
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

Page Write
single write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to 15 additional bytes. After each byte has been transmitted,
the CAT1021/22/23 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
Acknowledge Polling
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write opration, the
CAT1021/22/23 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
user to protect against inadvertent memory array
programming. If the WP pin is tied to V
memory array is protected and becomes read only. The
in the same manner as the write operation with one
exception, the R/W bit is set to one. Three different READ
The CAT1021/22/23 writes up to 16 bytes of data in a
Disabling of the inputs can be used to take advantage of
The Write Protection feature (CAT1021 only) allows the
The READ operation for the CAT1021/22/23 is initiated
BUS ACTIVITY:
SDA LINE
MASTER
S
BUS ACTIVITY:
R
S
T
A
T
SDA LINE
ADDRESS
MASTER
SLAVE
S
S
A
R
T
T
A
C
K
WRITE PROTECTION PIN (WP)
CC
ADDRESS (n)
ADDRESS
Figure 9. Page Write Timing
Figure 8. Byte Write Timing
, the entire
SLAVE
BYTE
READ OPERATIONS
http://onsemi.com
C
A
K
A
C
K
11
ADDRESS
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1021/22/23 in a single write cycle.
the start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
CAT1021 will accept both slave and byte addresses, but the
memory location accessed is protected from programming
by the device’s failure to send an acknowledge after the first
byte of data is received.
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
BYTE
DATA n
If the Master transmits more than 16 bytes before sending
When all 16 bytes are received, and the STOP condition
A
C
K
A
C
K
DATA n+1
DATA
C
A
K
C
A
K
P
O
S
T
P
DATA n+15
C
A
K
O
S
T
P
P