MAX697C/D Maxim Integrated, MAX697C/D Datasheet - Page 7

• Manufacturer Part Number: MAX697C/D
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX696, MAX697r

Specifications of MAX697C/D

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V to 5.5 V
• Undervoltage Threshold: Adj
• Overvoltage Threshold: Adjustable
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 70 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: Die
• Chip Enable Signals: Yes
• Maximum Power Dissipation: 600 mW
• Minimum Operating Temperature: 0 C
• Power Fail Detection: Yes
• Supply Current (typ): 300 uA
• Supply Voltage - Min: 3 V

low for 50ms after LL
repeated toggling of RESET even if the V
out and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock
for microprocessors takes several milliseconds to start.
Since most microprocessors need several clock cycles
to reset, RESET must be held low until the microproces-
sor clock oscillator has started. The power-up RESET
pulse lasts 50ms to allow for this oscillator startup time.
An inverted, active-high RESET output is also supplied.
The MAX696 issues a nonmaskable interrupt (NMI) to
the microprocessor when a power failure occurs. The
power line is monitored by two external resistors con-
nected to the power-fail input (PFI). When the voltage at
PFI falls below 1.3V, the power-fail output (PFO) drives
the processor’s NMI input low. An earlier power-fail
warning can be generated if the unregulated DC input
of the regulator is available for monitoring.
Figure 2. MAX696/MAX697 Block Diagram
(MAX697) CHIP-ENABLE INPUT
WATCHDOG INPUT
POWER-FAIL
INPUT
OSC SEL
OSC IN
LL
V
CC
IN
_______________________________________________________________________________________
IN
rises above 1.3V. This prevents
13
11
3
8
9
7
Microprocessor Supervisory Circuits
Power-Fail Detector
1.30V
V
BATT
(MAX696)
+
-
+
-
1
CC
+
-
power drops
WATCHDOG TRANSITION
TIMEBASE FOR RESET
RESET GENERATOR
WATCHDOG
DETECTOR
AND
5
The microprocessor drives the watchdog input (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin
once every 1.6 seconds to verify proper software execu-
tion. If a hardware or software failure occurs so that WDI
is not toggled, the MAX696 will issue a 50ms RESET
pulse after 1.6 seconds. This typically restarts the micro-
processor’s power-up routine. A new RESET pulse is
issued every 1.6 seconds until WDI is again strobed.
The watchdog output (WDO) goes low if the watchdog
timer is not serviced within its timeout period. Once
WDO goes low, it remains low until a transition occurs
at WDI while RESET is high. The watchdog timer fea-
ture can be disabled by leaving WDI unconnected.
OSC IN and OSC SEL also allow other watchdog timing
options, as shown in Table 1 and Figure 7.
BATT ON (MAX696)
WATCHDOG
TIMER
4
GROUND
12
15
16
6
14
10
2
LOW LINE
CHIP-ENABLE OUTPUT (MAX697)
RESET
RESET
WATCHDOG OUTPUT
V
POWER-FAIL OUTPUT
OUT
Watchdog Timer
(MAX696)
7