CY7C1018DV33-10VXI Cypress Semiconductor Corp, CY7C1018DV33-10VXI Datasheet - Page 4

IC SRAM 1MBIT 10NS 32SOJ

CY7C1018DV33-10VXI

Manufacturer Part Number
CY7C1018DV33-10VXI
Description
IC SRAM 1MBIT 10NS 32SOJ
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY7C1018DV33-10VXI

Memory Size
1M (128K x 8)
Package / Case
32-SOJ
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
10 ns
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.97 V
Maximum Operating Current
60 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3.3 V
Memory Configuration
128K X 8
Supply Voltage Range
3V To 3.6V
Memory Case Style
SOJ
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1963-5
CY7C1018DV33-10VXI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1018DV33-10VXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-05465 Rev. *E
AC Switching Characteristics
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
7. t
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
[9]
[9]
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
POWER
HZOE
Parameter
[6]
, t
HZCE
gives the minimum amount of time that the power supply should be at typical V
, and t
[10, 11]
HZWE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
CC
(typical) to the first access
Description
[8]
Over the Operating Range
[7, 8]
[7, 8]
[8]
[7, 8]
HZCE
is less than t
LZCE
, t
HZOE
is less than t
[5]
CC
LZOE
values until the first memory access can be performed.
Min.
100
10
10
, and t
3
0
3
0
8
8
0
0
7
5
0
3
HZWE
HZWE
–10 (Industrial)
and t
is less than t
SD
.
LZWE
Max.
for any given device.
10
10
10
5
5
5
5
CY7C1018DV33
Page 4 of 10
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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