CY62147EV30LL-45ZSXI Cypress Semiconductor Corp, CY62147EV30LL-45ZSXI Datasheet - Page 5

• Manufacturer Part Number: CY62147EV30LL-45ZSXI
• Description: IC SRAM 4MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62147EV30LL-45ZSXI

• Memory Size: 4M (256K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2073; CY62147EV30LL-45ZSXI

Thermal Resistance
Data Retention Characteristics
Over the Operating Range
Notes
Document Number: 38-05440 Rev. *J
V
I
t
t
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
14. Full device operation requires linear V
15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Parameter
CCDR
CDR
R
Parameter
DR
[14]
CE
BHE.BLE


[11]
[13]
2
JA
JC
such that when CE
OUTPUT
CE or
V
Parameters
CC
V
INCLUDING
V
Data retention current
Chip deselect to data retention time
Operation recovery time
CC
R
V
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
R1
R2
CC
JIG AND
TH
TH
SCOPE
for data retention
30 pF
Description
1
is LOW and CE
R1
Description
[11]
CC
R2
2
ramp from V
is HIGH, CE is LOW. For all other cases CE is HIGH.
Equivalent to: THEVENIN EQUIVALENT
V
t
CC(min)
CDR
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
Figure 5. Data Retention Waveform
Figure 4. AC Test Load and Waveforms
OUTPUT
DR
2.50 V
16667
15385
8000
1.20
to V
CC(min)
Rise Time = 1 V/ns
V
V
CC
IN
> 100 s or stable at V
Test Conditions
= 1.5 V, CE > V
> V
V
CC
DATA RETENTION MODE
GND
CC
– 0.2 V or V
R
TH
V
DR
10%
> 1.5V
CC
Conditions
CC(min)
– 0.2 V,
V
IN
ALL INPUT PULSES
90%
< 0.2 V
SB2
> 100 s.
3.0 V
1554
1103
1.75
645
/ I
[15, 16]
CCDR
spec. Other inputs can be left floating..
Package
CC
VFBGA
V
= V
CY62147EV30 MoBL
75
10
CC(min)
90%
CC(typ)
t
10%
R
Fall Time = 1 V/ns
, T
A
Min
1.5
45
= 25 °C.
–
0
Package
TSOP II
77
13
Typ
0.8
Unit
–
–
–



V
[12]
Page 5 of 16
Max Unit
–
7
–
–
C / W
C / W
Unit
1
A
ns
ns
and
V
®
[+] Feedback