CY7C1325G-133AXC Cypress Semiconductor Corp, CY7C1325G-133AXC Datasheet - Page 4

• Manufacturer Part Number: CY7C1325G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1325G-133AXC

• Memory Size: 4.5M (256K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Configurations
Pin Definitions
Document Number: 38-05518 Rev. *H
A0, A1, A
BW
GW
BWE
CLK
CE
CE
CE
OE
1
2
3
A,
Name
BW
B
asynchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input-clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
G
M
A
B
C
D
E
H
K
N
P
R
U
F
J
L
T
(continued)
Address inputs used to select one of the 256 K address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
A
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
NC/288M
NC/144M
[1:0]
NC/72M
2
1
1
V
V
V
V
V
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
and CE
DDQ
DDQ
DDQ
DDQ
DDQ
and CE
and CE
1
feed the 2 bit counter.
B
B
B
B
3
3
2
DQP
to select/deselect the device. ADSP is ignored if CE
DQ
DQ
DQ
DQ
to select/deselect the device. CE
to select/deselect the device. CE
CE
V
NC
NC
NC
NC
NC
NC
Figure 2. 119-ball BGA Pinout
2
A
A
A
A
DD
2
B
B
B
B
B
MODE
BW
V
V
V
V
V
V
V
V
V
NC
NC
A
A
A
A
3
SS
SS
SS
SS
SS
SS
SS
SS
SS
B
NC/36M
ADSP
ADSC
BWE
ADV
CLK
V
CE
V
V
GW
NC
OE
NC
NC
A1
A0
4
DD
DD
DD
1
Description
BW
V
V
V
V
V
V
V
V
V
NC
NC
NC
2
3
A
5
A
A
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
is sampled only when a new external address
is sampled only when a new external address
A
DQP
DQ
DQ
DQ
DQ
CE
V
NC
NC
NC
NC
NC
NC
A
A
A
A
A
6
DD
1
, CE
3
A
A
A
A
A
2
1
NC/576M
, and CE
NC/1G
is HIGH. CE
V
V
V
V
V
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
7
A
A
A
A
[A:B]
3
are sampled active.
and BWE).
1
CY7C1325G
is sampled only
Page 4 of 21
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