CY7C1338G-100AXC Cypress Semiconductor Corp, CY7C1338G-100AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C1338G-100AXC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1338G-100AXC

• Memory Size: 4M (128K x 32)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 205 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 4Mb
• Access Time (max): 8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 205mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 32b
• Number Of Words: 128K
• Memory Configuration: 128K X 32
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document Number: 38-05521 Rev. *F
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the processor
address strobe (ADSP) or the controller address strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
ADV
ADSP
ADSC
ZZ
DQs
V
V
V
V
MODE
NC
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
DD
SS
DDQ
SSQ
Name
synchronous
synchronous
synchronous
asynchronous
synchronous
C0
I/O ground Ground for the I/O circuitry.
I/O power
Ground
) is 6.5 ns (133-MHz device).
Power
supply
supply
Input-
Input-
Input-
Input-
Input-
static
I/O-
I/O
–
(continued)
Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
ZZ pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Power supply for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode pin has an internal pull-up.
No connects. Not Internally connected to the die.
No connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
1
is deasserted HIGH.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
Description
[A:D]
1
, CE
) inputs. A global write
1
, CE
[1:0]
2
CY7C1338G
, and CE
are also loaded
2
, CE
DD
Page 5 of 21
3
) and an
or left
3
[1:0]
are all
are
1
[+] Feedback