PSD834F2V-15J STMicroelectronics, PSD834F2V-15J Datasheet - Page 51

• Manufacturer Part Number: PSD834F2V-15J
• Description: IC FLASH 2MBIT 150NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V-15J

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2010-5

I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP space.
The topics discussed in this section are:
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■
■
■
■
General Port Architecture
The general architecture of the I/O Port block is
shown in
chitectures are shown in
Figure 31., page
for a port pin has been defined, that pin is no lon-
ger available for other purposes. Exceptions are
noted.
As shown in
an output multiplexer whose select signals are
driven by the configuration bits in the Control Reg-
isters (Ports A and B only) and PSDsoft Express
Configuration. Inputs to the multiplexer include the
following:
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■
■
■
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS0-ECS2) from the
CPLD.
Figure 26., page
Figure 26., page
61. In general, once the purpose
Figure 28., page 58
52. Individual Port ar-
52, the ports contain
Doc ID 10552 Rev 3
to
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note AN1171 for more detail.
Table 19., page 53
available on each port.
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following sections.
Input Macrocell, page
summarizes which modes are
PSD813F2V, PSD854F2V
Table 22., page 56
41.
shows
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