CY7C1370D-167AXC Cypress Semiconductor Corp, CY7C1370D-167AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1370D-167AXC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-167AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 167MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2135; CY7C1370D-167AXC

Pin Definitions
Introduction
Functional Overview
The CY7C1370D and CY7C1372D are synchronous-pipelined
burst NoBL SRAMs designed specifically to eliminate wait states
during write/read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the clock enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (t
Accesses can be initiated by asserting all three chip enables
(CE
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
Document Number: 38-05555 Rev. *K
TCK
V
V
V
NC
NC/(36M,72M,
144M, 288M,
576M, 1G)
ZZ
DD
DDQ
SS
Pin Name
1
, CE
3
are all asserted active, (3) the write enable input signal
2
, CE
3
) active at the rising edge of the clock. If clock
asynchronous
Power supply Power supply inputs to the core of the device.
JTAG-clock
I/O power
I/O Type
Ground
supply
CO
Input-
(continued)
–
–
) is 2.6 ns (250-MHz device).
X
can be used to conduct byte write
Clock input to the JTAG circuitry.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M and 1G densities.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to V
floating. ZZ pin has an internal pull down.
1
, CE
2
, CE
3
) and an
1
, CE
2
,
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tristate following the next clock rise.
Burst Read Accesses
The CY7C1370D and CY7C1372D have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the
Accesses
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQ
CY7C1372D). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
CY7C1372D) (or a subset for byte write operations, see Write
Pin Description
a,b,c,d
a,b,c,d
3
are all asserted active, and (3) the write signal WE is
/DQP
/DQP
section above. The sequence of the burst counter is
a,b,c,d
a,b,c,d
CY7C1370D, CY7C1372D
for CY7C1370D and DQ
for CY7C1370D & DQ
a,b
a,b
SS
Single Read
Page 8 of 29
/DQP
/DQP
or left
1
a,b
a,b
, CE
for
for
2
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