MAX820SEJE-T Maxim Integrated, MAX820SEJE-T Datasheet - Page 12

• Manufacturer Part Number: MAX820SEJE-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX792, MAX792L, MAX792M, MAX792R, MAX792S, MAX792T, MAX820, MAX820L, MAX820M, MAX820R, MAX820S, MAX820Tr

Specifications of MAX820SEJE-T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.75 V to 5.5 V
• Undervoltage Threshold: 2.85 V
• Overvoltage Threshold: 3 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: CDIP N
• Chip Enable Signals: Yes
• Maximum Power Dissipation: 800 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 150 uA
• Supply Voltage - Min: 2.75 V

default is 1.6s. Select alternative timeout periods by
connecting an external capacitor from SWT to GND
(see Selecting an Alternative Watchdog Timeout sec-
tion). When V
dog function is disabled.
WDO remains high if there is a transition or pulse at WDI
during the watchdog timeout period. The watchdog
function is disabled and WDO is a logic high when V
is below the reset threshold. If a system reset is desired
on every watchdog fault, simply diode-OR connect WDO
to MR (Figure 8). When a watchdog fault occurs in this
mode, WDO goes low, pulling MR low and causing a
reset pulse to be issued. As soon as reset is asserted,
the watchdog timer clears and WDO goes high. With
WDO connected to MR, a continuous high or low on WDI
will cause 200ms reset pulses to be issued every
1.6sec (SWT connected to V
asserted, if no transition occurs at WDI during the
watchdog timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next tran-
sition at WDI (Figure 7). A single additional flip-flop can
force the system into a hardware shutdown if there are
two successive watchdog faults (Figure 8). When the
MAX792/MAX820 are operated from a 5V supply, WDO
has a 2 x TTL output characteristic.
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog timeout period, WDPO will pulse low
for 1.7ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the flip-
flop’s Q output remains high after WDO goes low (Figure
8). If the watchdog timer is not reset by a transition at
Microprocessor and Nonvolatile
Memory Supervisory Circuits
Figure 7. WDI, WDO, and WDPO Timing Diagram
12
WDPO
WDO
WDI
V
CC
______________________________________________________________________________________
= 5V
CC
is below the reset threshold, the watch-
70ns
1.6s
Watchdog-Pulse Output
CC
). When reset is not
Watchdog Output
MIN 100ns (V
MIN 300ns (V
CC
CC
= 5V)
= 3V)
CC
WDI, WDO remains low and the next WDPO following a
second watchdog timeout period clocks a logic low to
the Q output, pulling MR low and causing the
MAX792/MAX820 latch in reset. If the watchdog timer is
reset by a transition at WDI, WDO will go high and the
flip-flop’s Q output will remain high. Thus a system
shutdown is only caused by two successive watchdog
faults.
The SWT input controls the watchdog timeout period.
Connecting SWT to V
watchdog timeout period. Select an alternative watch-
dog timeout period by connecting a capacitor between
SWT and GND. Do not leave SWT floating and do not
connect it to ground. The following formula determines
the watchdog timeout period:
Watchdog Timeout Period =
where k = 27 for V
This applies for capacitor values in excess of 4.7nF. If
the watchdog function is unused, connect SWT to V
Figure 8. Two consecutive watchdog faults latch the system in
reset.
REACTIVATE
V
Selecting an Alternative Watchdog Timeout Period
CC
+5V
k x (capacitor value in nF)ms
9
4.7k
0.1µF
MR
CC
MAX792
MAX820
= 3V, and k = 16.2 for V
GND
V
* FOR SYSTEM RESET ON EVERY
CC
CC
WATCHDOG FAULT, OMIT THE
FLIP-FLOP, AND DIODE–OR
CONNECT WDO TO MR.
12
3
RESET
WDPO
WDO
WDI
selects the internal 1.6sec
15
1
11
16
*
D
CLOCK
CLEAR
0.1µF
V
CC
Q
Q
CC
RESET
I/O
µP POWER
CONSECUTIVE
WATCHDOG
INDICATION
= 5V.
V
FAULT
TWO
CC
CC
.