CY7C1512V18-200BZC Cypress Semiconductor Corp, CY7C1512V18-200BZC Datasheet

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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words (CY7C1510V18), 9-bit words (CY7C1525V18), 18-bit words (CY7C1512V18), or 36-bit words (CY7C1514V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on ...

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... D [8:0] 22 Address A (21:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Write Write Address Reg Reg Register Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Address Reg Reg Register Control Logic Read Data Reg ...

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... Logic Block Diagram (CY7C1512V18 [17:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1514V18 [35:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 ...

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... Pin Configuration The pin configuration for CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 follow DOFF V V REF DDQ TDO TCK DOFF V V REF DDQ TDO TCK A Note 1. V /144M and V /288M are not connected to the die and can be tied to any voltage level Document #: 38-05489 Rev. *F ...

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... Pin Configuration (continued) The pin configuration for CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 follow /144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...

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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1510V18 arrays each for CY7C1525V18 arrays each 18) for CY7C1512V18, and arrays each 36) for CY7C1514V18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510V18 and CY7C1525V18, 21 address inputs for CY7C1512V18, and 20 address inputs for CY7C1514V18 ...

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... Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Pin Description Switching Characteristics on page 23. Switching Characteristics on page 23. output impedance are set to 0.2 x RQ, where resistor connected [x:0] ...

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... This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1512V18 has a port select input for each port. This using [17:0] enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K) ...

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... Delayed 50ohms Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 DLL These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum ...

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... Truth Table The truth table for CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 follow. Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...

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... L– – Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 [2, 8] Comments [ Comments – During the Data portion of a write sequence, all four bytes (D the device. L–H During the Data portion of a write sequence, all four bytes (D the device. – During the Data portion of a write sequence, only the lower byte (D into the device ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...

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... Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1-DR ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 0 Bypass Register Instruction Register ...

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... Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 38-05489 Rev. *F Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Min Max ALL INPUT PULSES 0.9V t TCYC t TDOX Page Unit ns MHz ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Value CY7C1525V18 CY7C1512V18 000 000 11010011010001100 11010011010010100 11010011010100100 Defines the type of ...

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... Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B ...

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... DDQ DOFF Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...

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... During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Ambient [15] Temperature ( 0°C to +70°C 1.8 ± 0.1V 1.4V to –40°C to +85°C ...

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... Over the Operating Range Parameter Description I Automatic Power down SB1 Current AC Electrical Characteristics [11] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Test Conditions Max V , 250MHz (x8) DD Both Ports Deselected, (x9) ≥ V ≤ 1/t , ...

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... Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Test Conditions T = 25° MHz 1.8V, V ...

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... For D0 data signal on CY7C1525V18 device 24 are specified with a load capacitance part (b) of CHZ CLZ state voltage. 25. At any voltage and temperature t is less than t CHZ Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Description [22] , BWS ) BWS ) 2 3 [24, 25] [24, 25] is the time that the power must be supplied above ...

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... Document #: 38-05489 Rev. *F WRITE WRITE READ NOP KHKH t CYC D31 D50 D51 D60 Q00 Q01 Q20 t CLZ t CQDOH t DOH CYC t CCQO t CQOH t CCQO CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 [26, 27, 28] WRITE NOP D61 Q21 Q40 Q41 t CHZ t CQD DON’T CARE UNDEFINED Page [+] Feedback ...

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... CY7C1525V18-250BZC CY7C1512V18-250BZC CY7C1514V18-250BZC CY7C1510V18-250BZXC CY7C1525V18-250BZXC CY7C1512V18-250BZXC CY7C1514V18-250BZXC CY7C1510V18-250BZI CY7C1525V18-250BZI CY7C1512V18-250BZI CY7C1514V18-250BZI CY7C1510V18-250BZXI CY7C1525V18-250BZXI CY7C1512V18-250BZXI CY7C1514V18-250BZXI 200 CY7C1510V18-200BZC CY7C1525V18-200BZC CY7C1512V18-200BZC CY7C1514V18-200BZC CY7C1510V18-200BZXC CY7C1525V18-200BZXC CY7C1512V18-200BZXC CY7C1514V18-200BZXC CY7C1510V18-200BZI CY7C1525V18-200BZI CY7C1512V18-200BZI CY7C1514V18-200BZI CY7C1510V18-200BZXI CY7C1525V18-200BZXI CY7C1512V18-200BZXI CY7C1514V18-200BZXI Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... CY7C1510V18-167BZXI CY7C1525V18-167BZXI CY7C1512V18-167BZXI CY7C1514V18-167BZXI Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... PIN 1 CORNER SEATING PLANE C Document #: 38-05489 Rev. *F CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 0.15(4X) NOTES : SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.65g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AD BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. +0.14 Ø0.50 (165X) -0. ...

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... Document History Page Document Title: CY7C1510V18/CY7C1525V18/CY7C1512V18/CY7C1514V18, 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05489 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 201260 See ECN NJY *A 257089 See ECN NJY *B 319496 See ECN SYT *C 403231 See ECN NXR Document #: 38-05489 Rev. *F ...

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... Document History Page Document Title: CY7C1510V18/CY7C1525V18/CY7C1512V18/CY7C1514V18, 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05489 *D 467290 See ECN NXR *E 2511080 See ECN VKN/AESA Updated Logic Block diagram , Updated Power-up sequence waveform and it’s *F 2549270 08/06/08 PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...