CY7C1480BV33-167AXC Cypress Semiconductor Corp, CY7C1480BV33-167AXC Datasheet
CY7C1480BV33-167AXC
Specifications of CY7C1480BV33-167AXC
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CY7C1480BV33-167AXC Summary of contents
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... GW when active LOW causes all bytes to be written. The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible ...
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... Logic Block Diagram – CY7C1480BV33 ( A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C WRITE REGISTER BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1482BV33 (4M x 18) ...
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... WRITE DRIVER WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480BV33 OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP H INPUT ...
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... Pin Configurations Figure 1. CY7C1480BV33 100-Pin TQFP Pinout DQP DQc DDQ V 5 SSQ SSQ V 11 DDQ CY7C1480BV33 ( DDQ V 21 SSQ SSQ 26 V DDQ DQP D 30 Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 Figure 2. CY7C1482BV33 100-Pin TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ DQ 75 ...
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... DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE NC/288M NC/144M A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 CY7C1480BV33 ( BWE CLK TDI A1 TDO TCK TMS CY7C1482BV33 ( BWE CLK ...
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... CE ADSC ADSP ADV 2 A NC/288M BWS BWE C G NC/144M NC/576M BWS NC/ DDQ DDQ DDQ DDQ DDQ DDQ MODE TDI CY7C1480BV33 BWS BWS BWS DQ BWS DQP DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP DQP DDQ DDQ ...
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... The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP condition. Power Supply Inputs to the Core of the Device. Ground for the Core of the Device. Ground for the IO Circuitry. serves as ground for the core and the IO circuitry. SS CY7C1480BV33 , CE , and CE are ...
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... The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 , and CE ) and an provide byte write capability that is described in the section 2 3 read/write truth table for CY7C1480BV33 follows. is HIGH. Asserting the Byte Write Enable input (BWE) with the selected 1 Byte Write (BW bytes. Bytes not selected during a Byte Write operation remain unaltered ...
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... DQs inputs. Doing so tri-states the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 provide a 2-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications ...
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... The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows. Truth Table Operation Add. Used Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Sleep Mode, Power Down ...
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... The read/write truth table for CY7C1480BV33 follows. Truth Table for Read/Write Function (CY7C1480BV33) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1480BV33 Page [+] Feedback ...
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... TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 RUN-TEST/ 0 IDLE Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 1 SELECT DR-SCA CAPTURE-DR CAPTURE-IR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE-DR UPDATE- CY7C1480BV33 1 SELECT IR-SCAN 0 0 SHIFT- EXIT1-IR 0 PAUSE- EXIT2- Page [+] Feedback ...
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... TAP Controller Block Diagram Selection TDI Circuitry TCK TM S Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 0 Bypass Register Selection Instruction Register Circuitry Identification Register Boundary Scan Register TAP CONTROLLER CY7C1480BV33 TDO Page [+] Feedback ...
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... OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1480BV33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
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... CS CH 10. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 Description Figure 3. TAP Timing TDIS t TDIH t TDOX DON’ UNDEFINED / ns CY7C1480BV33 Min Max Unit 50 20 MHz TDOV Page ...
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... Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1480BV33 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density ...
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... C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 Bit # 165-Ball P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480BV33 Bit # 165-Ball Bit # 165-Ball ID 37 C11 38 A11 39 A10 40 B10 ...
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... L11 W6 71 L10 J11 V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480BV33 Bit # 209-Ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 100 A8 101 B4 102 B3 103 C3 104 C4 ...
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... MAX CYC 6.0 ns cycle, 167 MHz /2). Undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480BV33 + 0.5V DD Ambient DDQ Temperature 0°C to +70°C 3.3V –5%/+10% 2.5V – –40°C to +85°C Min Max 3 ...
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... MHz 3. 2.5V DDQ 100 TQFP Test Conditions Package Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. CY7C1480BV33 Min Max Unit 120 245 245 245 135 165 FBGA 209 FBGA Unit Max Max Max ...
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... R = 317Ω 3.3V V OUTPUT DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1480BV33 ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) Page [+] Feedback ...
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... V AC Test Loads and Waveforms is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1480BV33 = 2.5V. Test conditions shown DDQ 200 MHz 167 MHz Unit Min Max Min ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1480BV33 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 Figure 4. Write Cycle Timing A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1480BV33 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE ...
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... The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 21 HIGH. Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 Figure 5. Read/Write Cycle Timing WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1480BV33 A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See the section 23. DQs are in High-Z when exiting ZZ sleep mode. Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 Figure 6. ZZ Mode Timing t RZZI DESELECT or READ Only High-Z DON’T CARE Truth Table on page 10 for all possible signal conditions to deselect the device. CY7C1480BV33 t ZZREC Page [+] Feedback ...
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... Speed Package (MHz) Ordering Code Diagram 167 CY7C1480BV33-167AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1482BV33-167AXC CY7C1480BV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1482BV33-167BZC CY7C1480BV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1482BV33-167BZXC CY7C1486BV33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × ...
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... CY7C1480BV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1482BV33-250AXC CY7C1480BV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1482BV33-250BZC CY7C1480BV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1482BV33-250BZXC CY7C1486BV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1486BV33-250BGXC CY7C1480BV33-250AXI 51-85050 100-pin Thin Quad Flat Pack ( ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1480BV33 1.40±0.05 12°±1° A SEE DETAIL (8X) ...
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... Package Diagrams (continued) Figure 8. 165-Ball FBGA ( 1.4 mm) TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 001-15145 Rev. *A CY7C1482BV33, CY7C1486BV33 0.15(4X) CY7C1480BV33 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 15.00±0.10 51-85165-*A Page [+] Feedback ...
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... Package Diagrams (continued) Figure 9. 209-Ball FBGA ( 1.76 mm) Document #: 001-15145 Rev. *A CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 51-85167-** Page [+] Feedback ...
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... Document History Page Document Title: CY7C1480BV33/CY7C1482BV33/CY7C1486BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 001-15145 Orig. of REV. ECN NO. Issue Date Change ** 1024385 See ECN VKN/KKVTMP New Data Sheet *A 2183566 See ECN VKN/PYRS © Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...