M93C46-WDW6TP STMicroelectronics, M93C46-WDW6TP Datasheet - Page 16

• Manufacturer Part Number: M93C46-WDW6TP
• Description: IC EEPROM 1KBIT 2MHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M93C46-WDW6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8 or 64 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 128 K x 8
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8655-2; M93C46-WDW6TP

Instructions
5.4
5.5
16/36
Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is
automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase
instruction before a Write Data to Memory (WRITE) instruction.
Figure 5.
1. For the meanings of An and Xn, please see
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in the
READY/BUSY status
ERASE, ERAL sequences
ERASE
ERASE
ALL
section.
S
Q
S
Q
D
D
Doc ID 4997 Rev 11
1 1
1
CODE
CODE
OP
0
OP
Table
1
0
1
An
0
ADDR
ADDR
5.,
M93C86, M93C76, M93C66, M93C56, M93C46
Xn X0
Table 6.
A0
and
BUSY
BUSY
Table
STATUS
STATUS
CHECK
CHECK
7..
READY
READY
AI00879B