M95640-WMN6T STMicroelectronics, M95640-WMN6T Datasheet
M95640-WMN6T
Specifications of M95640-WMN6T
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M95640-WMN6T Summary of contents
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... More than 40-year data retention ■ Enhanced ESD Protection ■ Packages ® – ECOPACK2 (RoHS-compliant and Halogen-free) April 2011 M95640 M95640-W M95640-R 64 Kbit serial SPI bus EEPROMs with high-speed clock UFDFPN8 (MB or MC) Doc ID 16877 Rev 15 M95640-DR SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width ...
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... Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/48 M95640, M95640-W, M95640-R, M95640- Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 16877 Rev 15 ...
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... M95640, M95640-W, M95640-R, M95640-DR 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE 6.7 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.8 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 Read Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10 Lock Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 ...
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... M95640-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9. Operating conditions (M95640 device grade Table 10. Operating conditions (M95640- Table 11. Operating conditions (M95640-R device grade Table 12. AC measurement conditions Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. ...
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... M95640, M95640-W, M95640-R, M95640-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 ...
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... They are accessed by a high-speed SPI-compatible bus. The devices are 64 Kbit devices organized as 8192 × 8 bits. The M95640-D also offers an additional page, named the Identification Page (32 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line can be used to store unique identification parameters and/or parameters specific to the production line ...
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... M95640, M95640-W, M95640-R, M95640-DR Table 1. Signal names Signal name HOLD Description Serial Clock Serial data input Serial data output Chip Select Write Protect Hold Supply voltage Ground Doc ID 16877 Rev 15 Description 7/48 ...
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... During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/48 M95640, M95640-W, M95640-R, M95640-DR must be held stable and within the specified valid range: CC Table 14) ...
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... M95640, M95640-W, M95640-R, M95640-DR 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write operations. ...
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... C line is pulled low (while the S line is pulled high): this will ensure that S and C do not become high at the same time, and so, that the t 10/48 M95640, M95640-W, M95640-R, M95640-DR R SDO SDI SCK ...
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... M95640, M95640-W, M95640-R, M95640-DR 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C) ...
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... Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The V voltage has to rise continuously from the minimum V CC defined in Table 9 12/48 M95640, M95640-W, M95640-R, M95640- (min), V (max)] range must be applied (see ...
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... M95640, M95640-W, M95640-R, M95640-DR 4.1.4 Power-down During power-down (continuous decrease in the V V operating voltage defined in CC ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...
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... The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-protected block size Status Register bits BP1 14/48 M95640, M95640-W, M95640-R, M95640-DR Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 ...
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... M95640, M95640-W, M95640-R, M95640-DR 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Address Register Figure 6. High Voltage Control Logic I/O Shift Register and Counter Doc ID 16877 Rev 15 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only ...
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... Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. 16/48 M95640, M95640-W, M95640-R, M95640-DR Description Write Enable Write Disable Read Status Register ...
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... M95640, M95640-W, M95640-R, M95640-DR Figure 7. Write Enable (WREN) sequence Instruction D High Impedance Q Doc ID 16877 Rev 15 Instructions AI02281E 17/48 ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: ● Power-up ● WRDI instruction execution ● WRSR instruction completion ● WRITE instruction completion. Figure 8. Write Disable (WRDI) sequence 18/48 M95640, M95640-W, M95640-R, M95640- send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance ...
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... M95640, M95640-W, M95640-R, M95640-DR 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the t The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0. 20/48 M95640, M95640-W, M95640-R, M95640- ...
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... M95640, M95640-W, M95640-R, M95640-DR Table 6. Protection modes W SRWD Mode Write protection of the Status Register signal bit 1 0 Status Register is Writable (if the WREN Software instruction has set the WEL bit protected The values in the BP1 and BP0 bits can be (SPM) changed 1 1 Hardware ...
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... The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed Write cycle is currently in progress. Figure 11. Read from Memory Array (READ) sequence High Impedance Q 1. Depending on the memory size, as shown in 22/48 M95640, M95640-W, M95640-R, M95640- Instruction 7 High Impedance ...
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... M95640, M95640-W, M95640-R, M95640-DR 6.6 Write to Memory Array (WRITE) As shown in Figure low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data ...
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... It is therefore recommended to write data by word (4 Bytes) at address 4*N (where integer) in order to benefit from the larger amount of Write cycles. The M95640-x and M95640-Dx devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device in multiples of 4-byte words. ...
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... M95640, M95640-W, M95640-R, M95640-DR If Chip Select (S) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the ID page from location 10d, the number of bytes should be less than or equal to 22d, as the ID page boundary is 32 bytes) ...
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... If Chip Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is shown in Figure 16. 26/48 M95640, M95640-W, M95640-R, M95640-DR Table 4), the Chip Select signal (S) is first driven low. The Doc ID 16877 Rev 15 ...
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... M95640, M95640-W, M95640-R, M95640-DR Figure 16. Read Lock Status sequence 6.10 Lock ID The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data input (D), and driving Chip Select (S) high ...
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... Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0. 28/48 M95640, M95640-W, M95640-R, M95640-DR Doc ID 16877 Rev 15 ...
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... M95640, M95640-W, M95640-R, M95640-DR 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Ambient operating temperature (device grade 3) A Table 10. Operating conditions (M95640-W) Symbol V Supply voltage CC Ambient operating temperature (device grade Ambient operating temperature (device grade 3) Table 11. Operating conditions (M95640-R device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 12. AC measurement conditions Symbol C Load capacitance ...
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... M95640, M95640-W, M95640-R, M95640-DR Table 13. Capacitance Symbol C Output capacitance (Q) OUT C Input capacitance (D) IN Input capacitance (other pins) 1. Sampled only, not 100% tested. Table 14. DC characteristics (M95640, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current ...
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... DC and AC parameters Table 15. DC characteristics (M95640-W, device grade 6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read Supply current (Write) CC0 Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... V RES voltage 1. If the application uses the M95640-R device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 15: DC characteristics (M95640-W, device grade 6) 2. Characterized only, not 100% tested. 3. 0.7 V with the device identified with process letter K. ...
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... DC and AC parameters Table 18. AC characteristics (M95640, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time CHSL ...
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... M95640, M95640-W, M95640-R, M95640-DR Table 19. AC characteristics (M95640-W products, device grade 6) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time ...
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... DC and AC parameters Table 20. AC characteristics (M95640-W products, device grade 3) Test conditions: V Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time CHSL ...
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... Write time Current products are identified by process letters P. 2. Preliminary data for the new products identified by process letter K. If the application uses the M95640-R device with 2.5 V < V < 5.5 V and -40 °C < T < +85 °C, please refer instead of the above table. ...
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... DC and AC parameters Figure 19. Serial input timing S tCHSL C tDVCH D Q Figure 20. Hold timing HOLD 38/48 M95640, M95640-W, M95640-R, M95640-DR tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 16877 Rev 15 tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c ...
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... M95640, M95640-W, M95640-R, M95640-DR Figure 21. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 16877 Rev 15 DC and AC parameters tSHSL tSHQZ AI01449f 39/48 ...
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... Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc Values in inches are converted from mm and rounded to 4 decimal digits. 40/48 M95640, M95640-W, M95640-R, M95640- ccc millimeters Typ Min Max 1.75 0.10 0.25 1.25 0.28 ...
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... M95640, M95640-W, M95640-R, M95640-DR Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 23. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits millimeters Typ. ...
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... (2) eee 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 42/48 M95640, M95640-W, M95640-R, M95640-DR millimeters Typ Min Max 0.550 0.450 0.600 0.020 0.000 0.050 ...
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... M95640, M95640-W, M95640-R, M95640-DR 11 Part numbering Table 25. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 640 = 64 Kbit (8192 × 8) 640 Kbit (8192 × 8) plus Identification Page Operating voltage blank = V = 4 2 1 (1) Package ...
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... I O 4.0 TSSOP8 connections added to DIP and SO connections M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and related characteristics added. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect Product List summary table added ...
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... A I and I parameters modified in CC CC1 (M95640-W, device grade Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz to 10 MHz in the device grade characteristics (M95640-W products, device grade 6) accordingly). Table 27: Available M95640x products (package, voltage range, temperature grade): /PB process letter added, /P process letter removed. ...
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... Section 11: Part 13 Added Table 4: M95640-DR instruction Identification Page, Section 6.9: Read Lock Figure 16: Read Lock Status Table 27: Available M95640-DR products (package, voltage range, temperature grade). Replaced Table 24. Doc ID 16877 Rev 15 Changes updated. Table 18: AC characteristics (M95640, updated. ...
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... Table 19 (1) - note under Table layout of Table 8 Added references to M95640-DR in titles of tables Deleted Table 26 Available M95640x products (package, voltage range, temperature grade) and Table 27 (package, voltage range, temperature grade). 15 Updated MLP8 package data. Doc ID 16877 Rev 15 Revision history Changes ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 48/48 M95640, M95640-W, M95640-R, M95640-DR Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...