SST49LF080A-33-4C-WHE Microchip Technology, SST49LF080A-33-4C-WHE Datasheet
SST49LF080A-33-4C-WHE
Specifications of SST49LF080A-33-4C-WHE
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SST49LF080A-33-4C-WHE Summary of contents
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... Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF080A device is offered in 32-lead TSOP and 32- lead PLCC packages. See Figures 2 and 3 for pin assign- ments and Table 1 for pin descriptions. ...
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... Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Registers General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chip-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ©2006 Silicon Storage Technology, Inc. 8 Mbit LPC Flash 2 SST49LF080A S71235-02-000 5/06 ...
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... Data Protection (PP Mode Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Software Data Protection (SDP SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PRODUCT ORDERING INFORMATION Valid combinations for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ©2006 Silicon Storage Technology, Inc. 3 Data Sheet S71235-02-000 5/06 ...
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... FIGURE 36: Software Product ID Command Sequences Flowchart (PP Mode FIGURE 37: Erase Command Sequence Flowchart (PP Mode FIGURE 38: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code FIGURE 39: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code ©2006 Silicon Storage Technology, Inc. 8 Mbit LPC Flash 4 SST49LF080A S71235-02-000 5/06 ...
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... TABLE 5: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 6: LPC Write Cycle TABLE 7: Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 8: General Purpose Inputs Register TABLE 9: Memory Map Register Addresses for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 10: Operation Modes Selection (PP Mode TABLE 11: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 12: DC Operating Characteristics (All Interfaces TABLE 13: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 14: Pin Capacitance (VDD=3.3V, Ta=25 ° ...
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... GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic MODE RST# CE Mbit LPC Flash SST49LF080A SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1235 B1.0 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A PIN ASSIGNMENTS A6 (GPI0) A5 (WP#) A4 (TBL#) DQ0 (LAD0) FIGURE 2: Pin Assignments for 32-lead PLCC (CE#) 4 MODE (MODE) 5 A10 (GPI4) 6 R/C# (LCLK RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP (TBL Designates LPC Mode FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) © ...
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... Circuit ground (0V reference) X This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode Unconnected pins Mbit LPC Flash SST49LF080A ) for PP mode and low (V ) for LPC mode T1.0 1235 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A DEVICE MEMORY MAPS TBL# WP# for Block 0~14 FIGURE 4: Device Memory Map ©2006 Silicon Storage Technology, Inc. 0FFFFFH Block 15 Boot Block 0F0000H 0EFFFFH Block 14 0E0000H 0DFFFFH Block 13 0D0000H 0CFFFFH Block 12 0C0000H 0BFFFFH Block 11 0B0000H 0AFFFFH Block 10 0A0000H 09FFFFH ...
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... CE# must be asserted one cycle before the start cycle to select the SST49LF080A for Read and Write operations. Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles ...
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... Device #0 Memory Access 1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H. ©2006 Silicon Storage Technology, Inc. Both TBL# and WP# pins must be set to their required pro- tection states prior to starting a Program or Erase opera- tion ...
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... This field is the least-significant nibble of the data byte. OUT This field is the most-significant nibble of the data byte. OUT In this clock cycle, the SST49LF080A has driven the bus to all then Float 1s and then floats the bus. This is the first part of the bus “turn- around cycle.” ...
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... IN then Float In this clock cycle, the host has driven the bus to all ‘1’s and then floats the bus. This is the first part of the bus “turnaround cycle.” Float then OUT The SST49LF080A takes control of the bus during this cycle. 0000 OUT The SST49LF080A outputs the values 0000, indicat- ing that it has received data or a flash command ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF080A device is in the internal Program operation, any attempt to read D[7] will produce the com- plement of the true data. Once the Program operation is completed, D[7] will produce true data ...
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... IDs. See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]’s strapping values. If there is a mis- match, the device will ignore the remainder of the cycle. TABLE 7: Multiple Device Selection Configuration Hardware ...
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... Silicon Storage Technology, Inc. JEDEC ID Registers The JEDEC ID registers identify the device as SST49LF080A and manufacturer as SST in LPC mode. See Table 9 for memory address locations for its respective JEDEC ID location. GPI_REG 0000 FFBC 0100H 0001 FFAC 0100H 0010 FF9C 0100H 0011 ...
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... SST49LF080A. See Table 23 for Reset timing parameters and Figure 17 for Reset timing diagram. Read The Read operation of the SST49LF080A device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 18, for further details. ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Data# Polling ( When the SST49LF080A device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data ...
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... Silicon Storage Technology, Inc. Software Data Protection (SDP) The SST49LF080A provides the JEDEC approved Soft- ware Data Protection scheme for all data alteration opera- tion, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. ...
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... PA = Program Byte address 4. SA for Sector-Erase Address for Block-Erase Address X 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer’ BFH, is read with A With SST49LF080A Device ID = 5BH, is read with Both Software ID Exit operations are equivalent ©2006 Silicon Storage Technology, Inc 2nd 3rd Cycle Cycle ...
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... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# 3rd Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] ...
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... Address 1 TAR A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Load Address in 8 Clocks 2 Clocks When internal write complete, the DQ 7 will equal to D7 Mbit LPC Flash SST49LF080A Start next Data TAR Sync Command TAR 0000b Dn[7:4] 1111b Tri-State 0000b 1 Clock 2 Clocks ...
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... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock Note: 1 ...
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... XXXXb XXXXb XXXXb 0000b Load Sector Address in 8 Clocks Load Data “30” Clocks Write the 6th command (target sector to be erased) to the device in LPC mode Sector Address 24 8 Mbit LPC Flash SST49LF080A Start next Command Data TAR Sync TAR 1010b 1111b ...
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... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle 0000b 011Xb LAD[3:0] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# ...
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... FIGURE 12: Register Readout Command Sequence (LPC Mode) ©2006 Silicon Storage Technology, Inc. Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks 26 8 Mbit LPC Flash SST49LF080A Start next TAR Sync Data 0000b TAR 1111b Tri-State 0000b D[3:0] D[7:4] ...
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... Mbit LPC Flash SST49LF080A ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 12 for the DC voltage and current speci- fications. Refer to Tables 16 through 19 and Tables 21 through 23 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “ ...
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... 0 =1500 µ 0 =-500 µ min, LFRAME# = IH, RC =3.3V, Ta=25 °C, f=1 Mhz, other pins open Mbit LPC Flash SST49LF080A and Address Input =V (PP mode) (PP Mode) TRC min Max and Address Input =V (PP mode) (PP Mode) TRC min , f=33 MHz, CE#=0 Max, All other inputs ≥ 0 ≤ ...
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... Mbit LPC Flash SST49LF080A TABLE 15: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 16: Clock Timing Parameters (LPC Mode) Symbol ...
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... FIGURE 14: Reset Timing Diagram (LPC Mode) ©2006 Silicon Storage Technology, Inc. =3.0-3.6V (LPC Mode reset procedure is performed during a Program or Erase operation. RSTE T PRST T KRST T RSTP T RSTF 30 8 Mbit LPC Flash SST49LF080A Min Max Units 1 ms 100 µs 100 µs 10 µs T17.0 1235 ...
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... Mbit LPC Flash SST49LF080A AC Characteristics TABLE 18: Read/Write Cycle Timing Parameters, V Symbol Parameter T Clock Cycle Time CYC T Data Set Up Time to Clock Rising SU T Clock Rising to Data Hold Time Clock Rising to Data Valid VAL T Byte Programming Time BP T Sector-Erase Time SE T Block-Erase Time ...
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... Silicon Storage Technology, Inc. V LCLK TEST T VAL LAD [3:0] LAD [3: OFF T SU Inputs Valid Value overdrive over V and V . Timing parameters must be met with no more over Mbit LPC Flash SST49LF080A 1235 F14 TEST MAX 1235 F15.0 Units V/ns T20.0 1235 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A TABLE 21: Read Cycle Timing Parameters, V Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time OE T OE# Low to Active Output ...
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... FIGURE 18: Read Cycle Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. T PRST T RSTF T RST T RC Row Address Column Address OLZ 34 8 Mbit LPC Flash SST49LF080A Row Address T RSTP Sector-/Block-Erase T RSTE or Program operation aborted T RSTC Chip-Erase aborted T RST 1235 F16.0 Row Address Column Address OHZ High-Z Data Valid 1235 F17 ...
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... Mbit LPC Flash SST49LF080A T RST RST# Row Address Addresses T AS R/C# OE# WE# DQ 7-0 FIGURE 19: Write Cycle Timing Diagram (PP Mode) Row Addresses R/C# WE# OE FIGURE 20: Data# Polling Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. Column Address CWH T OES Data Valid Column ...
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... FIGURE 21: Toggle Bit Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/C# OE# WE Byte-Program Address A = Most Significant Address MS FIGURE 22: Byte-Program Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. T OET 2AAA 5555 Mbit LPC Flash SST49LF080A D 1235 F20.0 BA Internal Program Starts DATA 1235 F21.0 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A A 14-0 (Internal A ) 5555 MS-0 R/C# OE Sector Address X FIGURE 23: Sector-Erase Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/C# OE Block Address X FIGURE 24: Block-Erase Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. 2AAA 5555 5555 2AAA 5555 5555 ...
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... DQ 7-0 FIGURE 25: Chip-Erase Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/ 7-0 Note: Device ID = 5BH for SST49LF080A FIGURE 26: Software ID Entry and Read (PP Mode) ©2006 Silicon Storage Technology, Inc. 2AAA 5555 5555 55 80 2AAA 5555 T WPH Mbit LPC Flash SST49LF080A 2AAA ...
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... Mbit LPC Flash SST49LF080A A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 FIGURE 27: Software ID Exit (PP Mode) V IHT INPUT V ILT AC test inputs are driven at V (0.9 V IHT points for inputs and outputs are V FIGURE 28: AC Input/Output Reference Waveforms TO DUT FIGURE 29: A Test Load Example © ...
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... Mbit LPC Flash Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: A Write Data: D Cycle: 4 Wait T BP Available for Next Byte 1235 F30.0 FIGURE 31: Byte-Program Flowchart (LPC Mode) 40 SST49LF080A IN IN S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A Command Sequence Address: 2AAAH Address: 2AAAH FIGURE 32: Erase Command Sequences Flowchart (LPC Mode) ©2006 Silicon Storage Technology, Inc. Block-Erase Sector-Erase Command Sequence Address: 5555H Address: 5555H Write Data: AAH Write Data: AAH Cycle: 1 Cycle: 1 Address: 2AAAH Write Data: 55H ...
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... Write Data: 55H Cycle: 2 Address: 5555H Write Data: F0H Cycle: 3 Wait T IDA Available for Next Command Note: X can but no other value Mbit LPC Flash SST49LF080A Address: XXXXH Write Data: F0H Cycle: 1 Wait T IDA Available for Next Command 1235 F32.0 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A FIGURE 34: Byte-Program Command Sequences Flowchart (PP Mode) ©2006 Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling ...
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... Silicon Storage Technology, Inc. Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed 44 8 Mbit LPC Flash SST49LF080A Data# Polling Byte- Program/Erase Initiated Read true data? Yes Program/Erase Completed 1235 F34.0 S71235-02-000 5/06 ...
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... Mbit LPC Flash SST49LF080A Software Product ID Entry Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 36: Software Product ID Command Sequences Flowchart (PP Mode) ©2006 Silicon Storage Technology, Inc. Software Product ID Exit ...
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... Write data: AAH Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: 50H Write data: 30H Address: BA Address Wait T Wait T BE Block erased Sector erased to FFH 46 8 Mbit LPC Flash SST49LF080A FFH 1235 F36.0 S71235-02-000 5/06 ...
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... Suffix1 SST49LF0x0A - XXX - XX Valid combinations for SST49LF080A SST49LF080A-33-4C-WHE SST49LF080A-33-4C-NHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. Suffix2 ...
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... Silicon Storage Technology, Inc. SIDE VIEW .112 .106 .029 .020 R. .040 x 30˚ R. .023 .030 MAX. .021 .013 .400 .032 BSC .026 .050 BSC .015 Min. .095 .075 .140 .125 48 8 Mbit LPC Flash SST49LF080A BOTTOM VIEW .530 .490 .032 .026 32-plcc-NH-3 S71235-02-000 5/06 ...
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... FIGURE 39: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH TABLE 24: Revision History Number 00 • Initial release (SST49LF080A previously released in data sheet S71206) 01 • Added statement that non-Pb devices are RoHS compliant to Features section • Updated Surface Mount Solder Reflow Temperature information • ...