DS2502S+ Maxim Integrated Products, DS2502S+ Datasheet
DS2502S+
Specifications of DS2502S+
Related parts for DS2502S+
DS2502S+ Summary of contents
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... EPROM partitioned into four 256-bit pages for randomly accessing packetized data Each memory page can be permanently write-protected to prevent tampering Device is an “add only” memory where additional data can be programmed into EPROM without disturbing existing data Architecture allows software to patch data by ...
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... DS2502P+ DS2502P/T&R DS2502P+T&R DS2502S DS2502S+ DS2502S/T&R DS2502S+T&R DS2502X1 + Indicates lead-free compliance. DESCRIPTION The DS2502 1Kb Add-Only Memory identifies and stores relevant information about the product to which it is associated. This lot- or product-specific information can be accessed with minimal interface- for example, a single port pin of a microcontroller. The DS2502 consists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1Kb of EPROM which is user-programmable ...
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... Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM Skip ROM. After a ROM function sequence has been successfully executed, the bus master may then provide any one of the memory function commands specific to the DS2502 (Figure 6). ...
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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8–Bit CRC Code MSB 1-WIRE CRC GENERATOR Figure 4 48–Bit Serial Number LSB MSB 8–Bit Family Code (09h) LSB MSB LSB ...
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... Page Address Redirection Bytes Page Address Redirection Byte has an FFH value, the data in the main memory that corresponds to that page is valid Page Address Redirection Byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one’ ...
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... All bits transferred to the DS2502 and received back by the bus master are sent least significant bit first. DS2502 MEMORY MAP Figure ...
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... MEMORY FUNCTION FLOW CHART Figure ...
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... MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) LEGEND: DECISION MADE BY THE MASTER DECISION MADE BYDS2502 ...
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... MEMORY FUNCTION FLOW CHART Figure 6 (cont’ ...
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... CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory will not have the 8-bit CRC available. ...
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... EPROM data and an 8-bit CRC that gets generated automatically at the end of each page. This type of read differs from the Read Memory command which simple reads each page until the end of address space is reached. The Read Memory command only generates an 8-bit CRC at the end of memory space that often might be ignored, since in many applications the user would store a 16-bit CRC with the data itself in each page of the 1024-bit EPROM data field at the time the page was programmed ...
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... Note that the initial pass through the Write Memory flow chart will generate an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte ...
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... If the CRC is incorrect, a reset pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally the data byte ...
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... DS2502 on a multidrop bus. Only the DS2502 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus ...
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DS2502 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure ...
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ROM FUNCTIONS FLOW CHART Figure ...
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... This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result) ...
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... DS2502 computes an 8-bit CRC for the command, address, and data bytes received for the Write Memory and the Write Status commands and then outputs this value to the bus master to confirm proper transfer. Similarly the DS2502 computes an 8-bit CRC for the command and address bytes received from the bus master for the Read Memory, Read Status, and Read Data/Generate 8-Bit CRC commands to confirm that these bytes have been received correctly ...
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READ/WRITE TIMING DIAGRAM Figure 11 Write-one Time Slot Write-zero Time Slot Read-data Time Slot RESISTOR MASTER DS2502 DS2502 SAMPLING WINDOW 60 s t < 120 s SLOT 1 s t < 15 s LOW1 1 s t ...
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PROGRAM PULSE TIMING DIAGRAM Figure ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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NOTES: 1. All voltages are referenced to ground external pullup voltage. PUP 3. Input load is to ground additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data ...
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REVISION HISTORY REVISION DATE Added note to Figure 10 that changed t Added VEPR specification. 12/09 Changed t to 960s maximum. RSTL Added notes 13 and 14. DESCRIPTION to 960s maximum. RSTL PAGES CHANGED ...