23A256-I/SN Microchip Technology, 23A256-I/SN Datasheet - Page 10

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23A256-I/SN

Manufacturer Part Number
23A256-I/SN
Description
IC SRAM 256KBIT 20MHZ 8SOIC
Manufacturer
Microchip Technology
Type
Synchronousr
Datasheets

Specifications of 23A256-I/SN

Memory Size
256K (32K x 8)
Package / Case
8-SOIC (3.9mm Width)
Format - Memory
RAM
Memory Type
SRAM
Speed
20MHz
Interface
SPI Serial
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Access Time
32 ns
Maximum Clock Frequency
16 MHz
Supply Voltage (max)
1.95 V
Supply Voltage (min)
1.5 V
Maximum Operating Current
10 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
1.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
23A256-I/SN
Manufacturer:
MCP
Quantity:
184
Part Number:
23A256-I/SN
Manufacturer:
MICROCHIP
Quantity:
2 000
23A256/23K256
2.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
TABLE 2-2:
FIGURE 2-7:
DS22100C-page 10
W/R = writable/readable.
MODE MODE
SCK
W/R
CS
SO
7
SI
Read Status Register Instruction
(RDSR)
W/R
6
0
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
5
0
0
1
High-Impedance
4
0
0
Instruction
2
3
0
0
3
2
0
0
4
1
0
1
HOLD
5
W/R
0
Preliminary
0
6
1
7
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
1 0 = Page mode
0 1 = Sequential mode
1 1 = Reserved
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
function to work properly. Setting HOLD to ‘1’ disables
feature.
Bits 1 through 5 are reserved and should always be set
to ‘0’.
See Figure 2-7 for the RDSR timing sequence.
7
8
6
9
Data from STATUS Register
10
5
11
4
© 2009 Microchip Technology Inc.
12
3
13
2
14
1
15
0

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