MAX819MESA Maxim Integrated, MAX819MESA Datasheet - Page 9

• Manufacturer Part Number: MAX819MESA
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX817, MAX817L, MAX817M, MAX818, MAX818L, MAX818M, MAX819, MAX819L, MAX819Mr

Specifications of MAX819MESA

• Number Of Voltages Monitored: 1
• Monitored Voltage: 4.4 V
• Undervoltage Threshold: 4.25 V
• Overvoltage Threshold: 4.5 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Narrow
• Chip Enable Signals: No
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 11 uA
• Supply Voltage - Min: 0 V

Designed for 5V systems, the MAX817/MAX818/
MAX819 provide a number of microprocessor (µP)
supervisory functions (see the Selector Guide on the
first page). Figure 2 shows the typical timing relation-
ships of the various outputs during power-up and
power-down with typical V
A µP’s reset input starts the µP in a known state. The
MAX817/MAX818/MAX819 µP supervisory circuits
assert a reset to prevent code-execution errors during
power-up, power-down, and brownout conditions.
RESET is guaranteed to be a logic low for 0V < V
V
tery (V
V
internal timer keeps RESET low for the reset timeout
period, t
(Figure 2).
If a brownout condition occurs (V
reset threshold), RESET goes low. Each time RESET is
asserted it stays low for at least the reset timeout peri-
od. Any time V
internal timer clears. The reset timer starts when V
returns above the reset threshold. RESET both sources
and sinks current.
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. On the MAX819, a logic
low on MR asserts reset. Reset remains asserted while
MR is low, and for t
Figure 2. Power-Up and Power-Down Timing
_______________Detailed Description
RST
CC
V
CE OUT**
V
V
RESET
V
PFO*
V
if V
OUT
** MAX818 ONLY.
CC
BATT
1V. Once V
*MAX817/MAX819 ONLY.
BATT
V
V
RP
V
BATT
BATT
BATT
. After this interval RESET returns high
= GND) RESET is guaranteed valid for
is greater than 1V. Without a backup bat-
General Timing Characteristics
V
CC
RST
t
+5V Microprocessor Supervisory Circuits
RP
Manual Reset Input (MAX819)
_______________________________________________________________________________________
CC
goes below the reset threshold the
RP
CE OUT FOLLOWS CE IN
exceeds the reset threshold an
(200ms) after it returns high.
CC
PFO FOLLOWS PFI
rise and fall times.
CC
RESET Output
drops below the
V
RST
V
BATT
RESET TO
CE OUT
DELAY**
CC
CC
<
During the reset timeout period (t
ignored if the battery freshness seal is enabled. MR has
an internal 63k
if not used. This input can be driven with TTL/CMOS-
logic levels or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function; external
debounce circuitry is not required. If MR is driven from
long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
Note that MR must be high or open to enable the bat-
tery freshness seal. Once the battery freshness seal is
enabled its operation is unaffected by MR.
The MAX817/MAX818/MAX819 battery freshness seal
disconnects the backup battery from internal circuitry
and OUT until it is needed. This allows an OEM to
ensure that the backup battery connected to BATT will
be fresh when the final product is put to use. To enable
the freshness seal on the MAX817 and MAX819:
1) Connect a battery to BATT.
2) Ground PFO.
3) Bring V
4) Bring V
Use the same procedure for the MAX818, but ground
CE OUT instead of PFO. Once the battery freshness
seal is enabled (disconnecting the backup battery from
internal circuitry and anything connected to OUT), it
remains enabled until V
Figure 3. Battery Freshness Seal Timing
there until reset is deasserted following the reset
timeout period.
CE OUT (MAX818)
(EXTERNALLY HELD AT 0V)
PFO (MAX817/MAX819)
(EXTERNALLY HELD AT 0V)
RESET
V
CC
CC
CC
V
RST
down again (Figure 3).
above the reset threshold and hold it
pull-up resistor, so it can be left open
CC
Battery Freshness Seal
is brought above V
CE OUT STATE LATCHED
AT 1/2 t
FRESHNESS SEAL ENABLED
PFO STATE LATCHED
AT 1/2 t
FRESHNESS SEAL ENABLED
t
RP
RP
RP
AND 3/4 t
AND 3/4 t
RP
), MR’s state is
RP
RP
,
,
RST
V
RST
.
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