PSD854F2V-12JI STMicroelectronics, PSD854F2V-12JI Datasheet
PSD854F2V-12JI
Specifications of PSD854F2V-12JI
Available stocks
Related parts for PSD854F2V-12JI
PSD854F2V-12JI Summary of contents
Page 1
... PROGRAMMABLE POWER MANAGEMENT May 2009 This is information on a product still in production but not recommended for new designs. PSD813F2V PSD854F2V for 8-bit MCUs, 3.3 V Figure 1. Packages ■ HIGH ENDURANCE: – 100,000 Erase/WRITE Cycles of Flash Memory – ...
Page 2
... PSD813F2V, PSD854F2V TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Register PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MCU Bus Interface JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 In-System Programming (ISP Power Management Unit (PMU DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DETAILED OPERATION Memory Blocks ...
Page 3
... PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O PORTS General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 3/109 ...
Page 4
... PSD813F2V, PSD854F2V PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Address Out Mode Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 JTAG In-System Programming (ISP Port Configuration Registers (PCR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Drive Select Register Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Data In Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output Macrocells (OMC OMC Mask Register ...
Page 5
... MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 REVISION HISTORY 108 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 5/109 ...
Page 6
... PSD813F2V, PSD854F2V SUMMARY DESCRIPTION The PSD8XXFX family of memory systems for mi- crocontrollers (MCUs) brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications ...
Page 7
... Figure 2. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 AD7 29 AD6 28 AD5 27 AD4 AI02858 7/109 ...
Page 8
... PSD813F2V, PSD854F2V Figure 3. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 8/109 Doc ID 10552 Rev 3 AD15 46 AD14 45 44 AD13 AD12 43 AD11 42 41 AD10 AD9 40 AD8 AD7 37 AD6 36 AD5 35 AD4 34 AI02857 ...
Page 9
... Figure 4. TQFP64 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 10 GND 11 PC3 12 PC2 13 PC1 14 PC0 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 48 CNTL0 47 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 AD7 36 AD6 35 AD5 34 AD4 33 AD3 AI09645b 9/109 ...
Page 10
... PSD813F2V, PSD854F2V PIN DESCRIPTION Table 2. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port ...
Page 11
... MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC1) output. PC1 19 I/O Input to the PLDs. TCK Input This pin can be configured as a CMOS or Open Drain output. Description 2 for the JTAG Serial Interface. 2 for the JTAG Serial Interface. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 11/109 ...
Page 12
... PSD813F2V, PSD854F2V Pin Name Pin Type PC2 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC2) output. PC2 18 I/O Input to the PLDs. This pin can be configured as a CMOS or Open Drain output. ...
Page 13
... Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from 77., page 107 for pin numbers on other package types. 2. These functions can be multiplexed with other functions. Description Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Table 75., page 105 and Table 13/109 ...
Page 14
... PSD813F2V, PSD854F2V Figure 5. PSD Block Diagram 14/109 Doc ID 10552 Rev 3 AI02861G ...
Page 15
... MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see the section entitled Examples, page Table 3. PLD I/O Name Decode PLD (DPLD) Complex PLD (CPLD) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V MCU Bus Interface 45. Product Inputs Outputs Terms 73 17 ...
Page 16
... PSD813F2V, PSD854F2V JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port C ...
Page 17
... PSD ATTRIBUTES PSD Fitter FIRMWARE AND FITTING HEX OR S-RECORD FORMAT *.OBJ FILE PSD Programmer PSDPro, or FlashLINK (JTAG) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V PSD TOOLS GENERATE C CODE SPECIFIC TO PSD FUNCTIONS USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ AND *.SVF FILES AVAILABLE FOR 3rd PARTY ...
Page 18
... PSD813F2V, PSD854F2V PSD REGISTER DESCRIPTION AND ADDRESS OFFSET Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is al- located by the user to the internal PSD registers. Table 6. I/O Port Latched Address Output Assignments (Note1) ...
Page 19
... Sector Size Sector Select Signal (Bytes) FS0 16K FS1 16K FS2 16K FS3 16K FS4 FS5 FS6 FS7 8 Sectors 64K Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V SRAM SRAM Size SRAM Select Signal (Bytes) CSBOOT0 256K CSBOOT1 CSBOOT2 CSBOOT3 4 Sectors 256K Signal RS0 19/109 ...
Page 20
... PSD813F2V, PSD854F2V Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. ...
Page 21
... PD@ PA XAAAh X555h 55h@ 80h@ AAh@ X555h XAAAh X555h 55h@ 80h@ AAh@ X555h XAAAh X555h 55h@ 20h@ XAAAh X555h PD@ PA 00h@ XXXXh Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Cycle 5 Cycle 6 Cycle 7 7 55h@ 30h@ 30h @ XAAAh SA next SA 55h@ 10h@ XAAAh X555h 21/109 ...
Page 22
... PSD813F2V, PSD854F2V INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly re- ceived and the time between two consecutive bytes is shorter than the time-out period. Some in- structions are structured to include READ opera- tions after the initial WRITE operations ...
Page 23
... Erase or Program instruction is being executed by the embedded algorithm. See the section entitled PROGRAMMING FLASH MEMORY, page 25 details. DQ7 DQ6 DQ5 DQ4 Data Toggle Error X Polling Flag Flag Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V for DQ3 DQ2 DQ1 DQ0 Erase Time out 23/109 ...
Page 24
... PSD813F2V, PSD854F2V Data Polling Flag (DQ7) When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the com- plement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruc- tion or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7 READ operation) ...
Page 25
... Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5). PSDsoft Express generates ANSI C code func- tions which implement these Data Polling algo- rithms. Figure 7. Data Polling Flowchart 7 READ DQ5 & DQ7 at VALID ADDRESS NO Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 7 still applies. However, the START DQ7 YES = DATA NO DQ5 = 1 ...
Page 26
... PSD813F2V, PSD854F2V Data Toggle Checking the Toggle Flag Bit (DQ6 method of determining whether a Program or Erase cycle is in progress or has completed. Figure Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be pro- grammed in Flash memory to check status ...
Page 27
... The Resume Sector Erase in- struction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or PRO- CSBOOT0-CSBOOT3) is High. (See 25. 9., page Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 21). This allows reading of data from an- 21.) Table Table 27/109 ...
Page 28
... PSD813F2V, PSD854F2V SPECIFIC FEATURES Flash Memory Sector Protect Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides addition- al data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. ...
Page 29
... SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 29/109 ...
Page 30
... PSD813F2V, PSD854F2V SECTOR SELECT AND SRAM SELECT Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size ...
Page 31
... Memory CSBOOT0-3 FS0-FS7 CS OE Bit 4 Bit 3 Primary Secondary FL_Data EE_Data can’ access Secondary Flash memory access Secondary Flash memory memory Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V SRAM Flash Memory Secondary SRAM Flash Memory Bit 2 Bit 1 Primary Secondary FL_Code EE_Code 0 = PSEN 0 = PSEN can’t can’ ...
Page 32
... PSD813F2V, PSD854F2V PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- PGR7) are inputs to the DPLD decoder and can be included ...
Page 33
... Macrocells Port C Input Macrocells Port D Inputs Page Register Macrocell AB Feedback Macrocell BC Feedback POWER Secondary Flash memory Program Status Bit Note: 1. The address inputs are A19-A4 in 80C51XA mode. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Number Input Name of Signals 1 A15-A0 16 CNTL2-CNTL0 3 RST 1 PDN 1 PA7-PA0 ...
Page 34
... PSD813F2V, PSD854F2V Figure 13. PLD Diagram 34/109 PORTS BUS INPUT PLD Doc ID 10552 Rev 3 I/O ...
Page 35
... JTAG Select signal (enables JTAG on Port C) ■ 2 internal Peripheral Select signals (Peripheral I/O mode). (INPUTS) (24) (8) (8) (8) (16) (3) (1) (3) (1) (1) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT FS0 3 FS1 3 FS2 3 FS3 8 PRIMARY FLASH MEMORY SECTOR SELECTS ...
Page 36
... PSD813F2V, PSD854F2V Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Se- lect (ECS0-ECS2), routed to Port D. ...
Page 37
... CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Maximum Borrowed Native Product Terms Product Terms Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Data Bit for Loading or Reading ...
Page 38
... PSD813F2V, PSD854F2V Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ■ McellAB0-McellAB7 all have three native product terms and may borrow up to six more ■ ...
Page 39
... Figure 16. CPLD Output Macrocell ARRAY AND BUS INPUT PLD Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 39/109 ...
Page 40
... PSD813F2V, PSD854F2V Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in 17., page 41. The Input Macrocells (IMC) are indi- vidually configurable, and can be used as a latch, register pass incoming Port signals prior to driving them onto the PLD input bus ...
Page 41
... Figure 17. Input Macrocell ARRAY AND BUS INPUT PLD Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 41/109 ...
Page 42
... PSD813F2V, PSD854F2V Figure 18. Handshaking Communication Using Input Macrocells 42/109 Doc ID 10552 Rev 3 ...
Page 43
... WR RD PSEN (Note (Note ) (Note 1 R/W E (Note ) (Note 1 R DBE (Note (Note ) (Note 1 R/W DS (Note ) (Note 1 R/W DS (Note ) (Note 1 R/W E (Note ) (Note Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 2 ADIO0 PA3-PA0 PD0 ALE A0 (Note ) 1 ) ALE A4 A3- ALE A0 (Note ) ALE A0 (Note ) ALE A0 (Note ) (Note ) 1 ...
Page 44
... PSD813F2V, PSD854F2V PSD Interface to a Multiplexed 8-Bit Bus Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. ...
Page 45
... Express Configuration. Table 17. Eight-Bit Data Bus BHE X X PSD PORT A ADIO PORT PORT CNTRL0 ) RD ( CNTRL1 ) BHE ( CNTRL2 ) PORT RST C ALE ( PD0 ) PORT D Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 25 show examples of the basic A0 D7-D0 0 Even Byte 1 Odd Byte 23:16 ] (OPTIONAL) AI02879C 45/109 ...
Page 46
... PSD813F2V, PSD854F2V 80C31 Figure 21 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Se- lect Enable (PSEN, CNTL2), Read Strobe (RD, Figure 21. Interfacing the PSD with an 80C31 ...
Page 47
... AD10 AD9 27 AD11 AD10 AD12 28 AD11 29 AD13 AD12 30 AD14 AD13 AD15 31 AD14 AD15 33 ALE A16 RESET Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V PSD 30 ADIO0 A16 ADIO1 PA0 32 28 ADIO2 PA1 33 27 ADIO3 PA2 34 25 ADIO4 PA3 35 24 ADIO5 PA4 36 23 ADIO6 PA5 ...
Page 48
... PSD813F2V, PSD854F2V Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 RST RESET 35 EA RESET Table 18. 80C251 Configurations 80C251 READ/WRITE Configuration Pins PSEN WR 2 PSEN only ...
Page 49
... A15 A15D11 28 A16 A16D12 A17 29 A17D13 30 A18 A18D14 31 A19 A19D15 32 PSEN PSEN WRL 33 ALE ALE RESET Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V PSD A4D0 30 ADIO0 A5D1 31 ADIO1 PA0 A6D2 32 ADIO2 PA1 33 A7D3 ADIO3 PA2 A8D4 34 AD104 PA3 A9D5 35 AD105 PA4 36 A10D6 ADIO6 ...
Page 50
... PSD813F2V, PSD854F2V 68HC11 Figure 25 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be Figure 25. Interfacing the PSD with a 68HC11 68HC11 RESET RESET 19 IRQ 18 XIRQ 2 MODB 34 PA0 33 PA1 32 PA2 43 PE0 44 PE1 45 PE2 ...
Page 51
... Note AN1171 for more detail. Table 19., page 53 available on each port. how and where the different modes are config- ured. Each of the port operating modes are de- scribed in the following sections. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 41. summarizes which modes are Table 22., page 56 shows 51/109 ...
Page 52
... PSD813F2V, PSD854F2V Figure 26. General I/O Port Architecture DATA OUT REG ADDRESS D ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT 52/109 DATA OUT Q ADDRESS Q DATA Doc ID 10552 Rev 3 PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT ...
Page 53
... The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. Port A Port B Yes Yes Yes No Yes Yes (A7 – (A15 – 8) Yes Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Port C Port D Yes Yes No No Yes No No Yes Yes Yes No No Yes Yes ...
Page 54
... PSD813F2V, PSD854F2V Table 20. Port Operating Mode Settings Defined in Mode PSDabel MCU I/O Declare pins only PLD I/O Logic equations Data Port (Port A) N/A Address Out Declare pins only (Port A,B) Address In Logic for equation (Port A,B,C,D) Input Macrocells Peripheral I/O Logic equations (Port A) (PSEL0 & ...
Page 55
... Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is en- abled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or PSEL1 is not active. PSEL DATA BUS Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 27 PA0 - PA7 AI02886 55/109 ...
Page 56
... PSD813F2V, PSD854F2V JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). You can multiplex JTAG operations with other functions on Port C because In-System Programming (ISP) is not per- formed in normal Operating mode. For more infor- mation on the JTAG Port, see the section entitled ...
Page 57
... WRITE – loading macrocells flip-flop WRITE/READ – prevents loading into a given A,B,C macrocell A,B,C READ – outputs of the Input Macrocells A,B,C READ – the output enable control of the port driver Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Bit 2 Bit 1 Bit 0 Slew Slew Slew Rate Rate ...
Page 58
... PSD813F2V, PSD854F2V Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See the section en- titled PLDS, page 33. Enable Out The Enable Out register can be read by the MCU. ...
Page 59
... Pin PC7 may be configured as the DBE input in certain MCU bus interfaces. DATA OUT REG. DATA OUT SPECIAL FUNCTION READ MUX P D DATA IN B DIR REG Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V PORT C PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL SPECIAL FUNCTION CONFIGURATION BIT for AI02888B 59/109 ...
Page 60
... PSD813F2V, PSD854F2V Port D – Functionality and Structure Port D has three I/O pins. See Figure ure 31., page 61. This port does not support Ad- dress Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions: ■ MCU I/O Mode ■ ...
Page 61
... Direction Register. (See Figure 31.) ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 AI02890 61/109 ...
Page 62
... PSD813F2V, PSD854F2V POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ■ All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design ...
Page 63
... CLR PD APD COUNTER EDGE PD DETECT Memory Access Recovery Time Access Time to Normal Access 1 No Access ) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Port Function Pin Level No Change No Change Undefined Tri-State Tri-State EEPROM SELECT FLASH SELECT PLD SRAM SELECT POWER DOWN ( PDN ) SELECT AI02891 ...
Page 64
... PSD813F2V, PSD854F2V For Users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compati- ble) in your design, and you wish to use the Pow- er-down mode, you must not connect the E clock to CLKIN (PD1). You should instead connect a crystal oscillator to CLKIN (PD1) ...
Page 65
... Powers-up the PLD when Turbo Bit is ’0.’ Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 65/109 ...
Page 66
... PSD813F2V, PSD854F2V PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A ...
Page 67
... During a Flash memory Program or Erase cycle, Reset (RESET) termi- nates the cycle and returns the Flash memory to the Read Mode within a period OPR Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V period is needed before the device OPR 34 shows the I/O pin, register and ramps up to operat- ...
Page 68
... PSD813F2V, PSD854F2V Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 and PMMR2 ...
Page 69
... System-Configuration (ISC) commands. A defini- tion of these JTAG In-System-Configuration (ISC) commands and sequences is defined in a supple- mental document available from ST. This docu- ment is needed only as a reference for designers who use a FlashLINK to program their PSD. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Table for bit definition. */ 69/109 ...
Page 70
... PSD813F2V, PSD854F2V JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD sig- nals instead of having to scan the status out seri- ally using the standard JTAG channel ...
Page 71
... Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 71/109 ...
Page 72
... PSD813F2V, PSD854F2V AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD: ❏ DC Electrical Specification ❏ AC Timing Specification ■ PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing ■ MCU Timing – READ Timing – ...
Page 73
... Freq ALE + % PLD x 2mA/MHz x Freq PLD + #PT x 400µA/PT) = 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz + 0.15 x 1.5mA/MHz x 4 MHz + 2mA/MHz x 8 MHz + 45 x 0.4mA/PT) = 45µ 18mA) = 45µA + 0.1 x 42.9 = 45µA + 4.29mA = 4.34mA Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V (ac (dc 73/109 ...
Page 74
... PSD813F2V, PSD854F2V Table 37. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report total product terms ...
Page 75
... Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi- Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Min. Max. Unit –65 125 °C 235 °C –0.6 7.0 V – ...
Page 76
... PSD813F2V, PSD854F2V DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 39. Operating Conditions (5V devices) Symbol ...
Page 77
... OUT ) Figure 38. AC Measurement Load Circuit 1.5V Device Under Test AI03103b INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM DON'T CARE OUTPUTS ONLY Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 2 Max. Unit Typ 2.01 V 195 (Including Scope and Jig Capacitance) AI03104b ...
Page 78
... PSD813F2V, PSD854F2V Table 45. DC Characteristics (5V devices) Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO Program V Output Low Voltage ...
Page 79
... MHz During Flash memory WRITE/Erase Only Read only MHz MHz is valid at or below 0.2V –0.1. V IL1 CC IH1 for the PLD current calculation. tER Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Min. Typ. Max. 0.3 1.5 2.2 0.01 0.1 0.15 0.45 2.9 2.99 2.7 2.8 – ...
Page 80
... PSD813F2V, PSD854F2V Table 47. CPLD Combinatorial Timing (5V devices) Symbol Parameter CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output Enable CPLD Input to CPLD t ER Output Disable CPLD Register Clear t ARP or Preset Delay CPLD Register Clear t ARPW or Preset Pulse Width ...
Page 81
... Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1 CLCL -70 -90 Min Max Min Max +t ) 40.0 30. –10) 66.6 43. 83.3 50. Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V AI02860 -15 Fast Turbo PT Off Min Max Aloc 25.00 31.25 35. Slew Unit 1 rate MHz MHz MHz – 81/109 ...
Page 82
... PSD813F2V, PSD854F2V Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f ) CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time CH t Clock Low Time ...
Page 83
... Figure 42. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 43. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT tARPW tARP tCHA tCLA tSA tHA tCOA Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V AI02864 AI02859 83/109 ...
Page 84
... PSD813F2V, PSD854F2V Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/(t SA External Feedback Maximum Frequency f Internal 1/(t MAXA SA Feedback (f ) CNTA Maximum Frequency 1/(t CHA Pipelined Data Input Setup t SA Time Input Hold t HA Time Clock Input ...
Page 85
... Minimum Clock t MINA Period -12 -15 Min Max Min +t ) 21.7 SA COA +t –10) 27.8 COA +t ) 33.3 CHA CLA 1 CNTA Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V -20 PT Turbo Aloc Off Max Min Max 19.2 16.9 23.8 20 Slew Unit Rate MHz MHz MHz ns ns ...
Page 86
... PSD813F2V, PSD854F2V Figure 44. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 53. Input Macrocell Timing (5V devices) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL NIB Input to Combinatorial ...
Page 87
... Page Mode or 80C51XA in Burst Mode. AVLX LXAX 1 t AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t THEH ADDRESS OUT Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V DATA VALID DATA VALID t RHQX tRHQZ t EHEL t ELTL AI02895 87/109 ...
Page 88
... PSD813F2V, PSD854F2V Table 55. READ Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-Bit Bus t RLQV RD or PSEN to Data Valid ...
Page 89
... RD timing has the same timing as DS, LDS, and UDS signals. -12 Conditions Min Max Min Max Min Max (Note ) (Note ) 3 120 (Note ) 120 5 35 (Note ) 2 45 (Note ) 1 0 (Note ) (Note ) (Note ) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V -15 -20 Turbo Unit Off 150 200 + 20 ns 150 200 89/109 ...
Page 90
... PSD813F2V, PSD854F2V Figure 46. WRITE Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 90/109 t AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT Doc ID 10552 Rev 3 DATA VALID DATA VALID t DVWH t WHDX ...
Page 91
... TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. -70 Conditions Min Max Min Max Min Max (Note ) 1 7 (Note ) 1,3 8 (Notes ) 3 12 (Note ) 3 25 (Note ) 3 4 (Note ) 3 31 (Note ) 3 6 (Note ) 3,6 0 (Note ) 3 (Note ) 3,5 (Notes ) 2 (Note ) 3,4 (Notes ) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V -90 -15 Unit 91/109 ...
Page 92
... PSD813F2V, PSD854F2V Table 58. WRITE Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH t WR Data Hold Time WHDX ...
Page 93
... WHWLO t DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) Q7VQV Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Parameter (pre-programmed) 2 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Min. Typ. Max. 8 ...
Page 94
... PSD813F2V, PSD854F2V Figure 47. Peripheral I/O READ Timing ALE/AS A/D BUS CSI RD Table 61. Port A Peripheral Data Mode READ Timing (5V devices) Symbol Parameter Address Valid to Data t AVQV–PA Valid t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode ...
Page 95
... Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A. -12 Conditions Min Max Min Max Min Max 3 (Note ) 1,4 (Notes ) (Note ) 1 (Note ) ADDRESS tWLQV (PA) Conditions 2 (Note ) 5 (Note ) 2 (Note ) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V -15 -20 Turbo Off DATA OUT tWHQZ (PA) tDVQV (PA) PORT A ...
Page 96
... PSD813F2V, PSD854F2V Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices) Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV– Invalid to Port A Tri-state WHQZ–PA Note has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). ...
Page 97
... Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. ISCCH t ISCCL t t ISCPSU ISCPH Conditions 1 (Note ) 1 (Note ) 1 (Note ) 2 (Note ) 2 (Note ) 2 (Note ) Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V t ISCPZV t ISCPCO t ISCPVZ AI02865 -70 -90 -15 Min Max Min Max Min Max 240 240 240 240 240 ...
Page 98
... PSD813F2V, PSD854F2V Table 68. ISC Timing (3V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for t ISCCL PLD) t Clock (TCK, PC1) Frequency (PLD only) ISCCFP ...
Page 99
... PACK® packages, depending on their level of en- vironmental compliance. Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. ECOPACK product status are available at: www.st.com. ECO- ® PACK Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V ® specifications, grade definitions and trademark 99/109 ...
Page 100
... PSD813F2V, PSD854F2V Table 71. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0.88 L1 1.60 α 100/109 mm Min. Max. Typ. 2.35 0.25 1.80 2.10 0.079 0.22 0.38 0.11 0.23 13.15 13.25 0.520 9.95 10.05 0.394 – ...
Page 101
... Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V A1 A2 D3/ inches Typ. Min. Max. 0.165 0.180 0.100 0.110 – 0.036 0.013 0.021 0.026 0.032 0.0097 0.0103 ...
Page 102
... PSD813F2V, PSD854F2V Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale. 102/109 Doc ID 10552 Rev ...
Page 103
... Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V inches Min. Max. 0.056 0.061 0.003 0.005 0.054 0.057 0.0° 7.0° 0.013 0.015 0.006 0.626 0.634 0.550 0.552 0.470 ...
Page 104
... PSD813F2V, PSD854F2V PART NUMBERING Table 74. Ordering Information Scheme Example: Device Type PSD8 = 8-bit PSD with Register Logic PSD9 = 8-bit PSD with Combinatorial Logic SRAM Capacity Kbit 5 = 256 Kbit Flash Memory Capacity Mbit (128K Mbit (256K x 8) 2nd Flash Memory 2 = 256 Kbit Flash memory + SRAM ...
Page 105
... PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 AD3 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Pin Assignments 27 AD4 28 AD5 29 AD6 30 AD7 AD8 33 AD9 34 AD10 35 AD11 36 AD12 37 AD13 38 ...
Page 106
... PSD813F2V, PSD854F2V APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 76. PLCC52 Connections (Figure 3) Pin Number Pin Assignments 106/109 Pin Number GND PB5 PB4 PB3 PB2 PB1 PB0 PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 ...
Page 107
... PC5 GND GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND GND PA2 PA1 PA0 AD0 AD1 N/D AD2 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V Pin Assignments 33 AD3 34 AD4 35 AD5 36 AD6 37 AD7 AD8 41 AD9 42 AD10 43 AD11 AD12 44 45 AD13 46 AD14 ...
Page 108
... PSD813F2V, PSD854F2V REVISION HISTORY Table 78. Document Revision History Date Version 04-Jun-04 1.0 First Edition (3V split from original) Removed PSD853F2V and PSD833F2V root part numbers. Updated Table 1 to remove PSD813F3, PSD813F4, PSD833F2, PSD834F2, and PSD853F2. Updated Table 74 to remove options not mentioned in the datasheet. ...
Page 109
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 109/109 ...