MAX6454UT44S-T Maxim Integrated, MAX6454UT44S-T Datasheet - Page 7

• Manufacturer Part Number: MAX6454UT44S-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6453, MAX6454, MAX6455, MAX6456r

Specifications of MAX6454UT44S-T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 1.8 V to 5 V
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 7 uA
• Supply Voltage - Min: 1 V

To minimize data loss and speed system recovery/test,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6455/
MAX6456 MR input allows the same pushbutton (Figure
4) to control both the interrupt and hard reset functions.
If the pushbutton is closed for less than the extended
setup timeout period, the processor is only interrupted
(MROUT). If the system still does not respond properly,
the pushbutton can be closed for the full extended
setup timeout period to hard reset the processor
(RESET). If desired, connect a LED to the RESET output
to turn off (or on) to signify when the pushbutton is
closed long enough for a hard reset (the same LED can
be used as the front panel power-on display).
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 5, the
open-drain output can be connected to voltages from 0
to 6V.
Figure 3. Calculating The Monitored Threshold Voltages
µP Supervisors with Separate V
R2
R1
V
V
MON_TH
MON_TH
Applications Information
= 0.63 x (R1 + R2) / R2
Interfacing to Other Voltages
_______________________________________________________________________________________
RSTIN
GND
MAX6453
MAX6455
for Logic Compatibility
Interrupt Before Reset
RESET
V
CC
V
CC
Generally, the pullup resistor connected to the RESET
connects to the supply voltage being monitored at the
IC’s V
open-drain output to level-shift from the monitored sup-
ply to reset circuitry powered by some other supply
(Figure 5). Keep in mind that as the supervisor’s V
decreases toward 1V, so does the IC’s ability to sink
current at RESET (RESET is pulled high as V
toward 0). The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
When V
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to
undetermined voltages. This presents no problem in
most applications, because most µPs and other circuit-
ry do not operate with V
In applications where RESET must be valid down to 0V,
add a pulldown resistor between RESET and GND for
the push/pull outputs. The resistor sinks any stray leak-
age currents, holding RESET low (Figure 6). The value
of the pulldown resistor is not critical; 100kΩ is large
enough not to load RESET and small enough to pull
RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
In addition to issuing a reset to the µP during power-up,
power-down and brownout conditions, these supervisors
are relatively immune to short duration falling transients
(glitches). The graph Maximum Transient Duration vs.
Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative
going pulse applied to V
reset threshold (V
tude indicated (reset-threshold overdrive). As the mag-
nitude of the transient increases (V
below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V
goes 100mV below the reset threshold and lasts 20µs
or less does not cause a reset pulse to be issued.
Ensuring a Valid RESET Down to V
Manual Reset Outputs
CC
CC
pin. However, some systems might use the
falls below 1V, RESET current-sinking capa-
TH
) and ending below it by the magni-
CC
CC
CC
below 1V.
, starting above the actual
Transient Immunity
Reset and
(Push-Pull RESET )
CC
CC
transient that
goes further
CC
CC
decays
= 0V
CC
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