CY7C009-15AXC Cypress Semiconductor Corp, CY7C009-15AXC Datasheet
CY7C009-15AXC
Specifications of CY7C009-15AXC
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CY7C009-15AXC Summary of contents
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... CY7C018/01964K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells that allow simultaneous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power [1] • ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View CY7C009 (128K x 8) CY7C008 (64K CY7C008/009 CY7C018/019 ...
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Pin Configurations (continued) 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [6] A16L 12 VCC ...
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... DC Input Voltage ......................................... –0.5V to +7.0V Notes: 7. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C009 and CY7C019 only. Document #: 38-06041 Rev. *D Chip Enable (CE is LOW when CE 1R Read/Write Enable ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH (V =Min –4.0 mA Output LOW Voltage OL (V =Min +4.0 mA Input HIGH Voltage IH V ...
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AC Test Loads and Waveforms 893Ω OUTPUT 347Ω (a) Normal Load (Load 1) AC Test Loads (Applicable to -12 only 50Ω 50Ω 0 OUTPUT C V (a) ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [14 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [19] BUSY TIMING t BUSY LOW from Address Match BLA t BUSY HIGH from Address Mismatch BHA t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC t ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access DATA OUT I CC CURRENT I SB [22, 24, 25, 26] Read ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [31 R/W NOTE 33 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 27. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009/19 R/W L INT R t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE FFFE (1FFFE for CY7C009/19 R/W R INT L t INS Left Side Clears INT ...
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... CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for the right port and the second-highest memory location (FFFE for the CY7C008/18, 1FFFE for the CY7C009/19) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 43. A and A , 1FFFF/1FFFE for the CY7C009/019. 0L–16L 0R–16R 44. If BUSY = L, then no change. R 45. If BUSY = L, then no change. ...
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... Ordering Code [1] 12 CY7C008-12AC 15 CY7C008-15AC CY7C008-15AXC 20 CY7C008-20AC 128K x 8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C009-12AC 15 CY7C009-15AC CY7C009-15AXC 20 CY7C009-20AC CY7C009-20AI 64K x 9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C018-12AC 15 CY7C018-15AC 20 CY7C018-20AC 128K x 9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code ...
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... Document #: 38-06041 Rev. *D © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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... Change from Spec number: 38-00665 to 38-06041 OOR Change pin 85 from BUSYL to BUSYR (pg. 3) RBI Power up requirements added to Maximum Ratings Information YDT Removed cross information from features section YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008-15AXC, CY7C009-15AXC CY7C008/009 CY7C018/019 Page ...