CAT25320LI-G ON Semiconductor, CAT25320LI-G Datasheet - Page 6

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CAT25320LI-G

Manufacturer Part Number
CAT25320LI-G
Description
IC EEPROM 32KBIT 10MHZ 8DIP
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT25320LI-G

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
32K (4K x 8)
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Organization
4 K x 8
Interface Type
SPI
Maximum Clock Frequency
5 MHz
Access Time
75 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
25320LI-G

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT25320LI-G
Manufacturer:
ON Semiconductor
Quantity:
20
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The CAT25320 device powers up into a write disable
SCK
SO
CS
SI
SCK
SO
CS
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
0
0
Figure 3. WREN Timing
WRITE OPERATIONS
0
0
Figure 4. WRDI Timing
http://onsemi.com
0
0
HIGH IMPEDANCE
0
0
HIGH IMPEDANCE
6
0
0
Write Enable and Write Disable
Status Register WEL bit are set by sending the WREN
instruction to the CAT25320. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
1
The internal Write Enable Latch and the corresponding
The internal write enable latch is reset by sending the
1
1
0
0
0

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