CAT24C64LI-G ON Semiconductor, CAT24C64LI-G Datasheet - Page 4

• Manufacturer Part Number: CAT24C64LI-G
• Description: IC EEPROM 64KBIT 400KHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT24C64LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Density: 64Kb
• Interface Type: Serial (I2C)
• Organization: 8Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 2mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C64LI-G

Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after V
power down into Reset mode when V
POR trigger level. This bi-directional POR behavior
protects the device against ‘brown-out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A
that must be matched by the corresponding Slave address
bits. The Address inputs are hard-wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally.
Functional Description
(I
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C64
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
0
2
Each CAT24C64 incorporates Power-On Reset (POR)
The CAT24C64 supports the Inter-Integrated Circuit
C) Bus protocol. The protocol relies on the use of a Master
, A
1
and A
CC
2
: The Address inputs set the device address
exceeds the POR trigger level and will
SDA
SCL
CONDITION
START
CC
1
drops below the
Figure 3. Slave Address Bits
0
Figure 2. Start/Stop Timing
http://onsemi.com
1
0
4
DEVICE ADDRESS
A
I
connected to the V
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
condition and then broadcasting an 8-bit Slave address. For
the CAT24C64, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A
the logic state of the similarly named input pins. The R/W
bit tells the Slave whether the Master intends to read (1) or
write (0) data (Figure 3).
Acknowledge
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
2
2
C Bus Protocol
The 2-wire I
An SDA transition while SCL is HIGH creates a START
The Master addresses a Slave by creating a START
During the 9
A
1
A
0
th
2
R/W
C bus consists of two lines, SCL and SDA,
clock cycle following every byte sent to the
CONDITION
STOP
CC
supply via pull-up resistors. The
2
, A
1
and A
0
, must match