AT24C02C-SSHM-T Atmel, AT24C02C-SSHM-T Datasheet - Page 6

• Manufacturer Part Number: AT24C02C-SSHM-T
• Description: IC EEPROM 2KBIT 1MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT24C02C-SSHM-T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 550ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see
periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The Atmel
up and (b) after the receipt of the STOP bit and the completion of any internal operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset
by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by
stop bit condition as shown below. The device is ready for next communication after above steps have been
completed.
Figure 3-1.
SCL
SDA
Atmel AT24C02C
Start bit
Software reset
Figure 5-3 on page
1
®
AT24C02C features a low-power standby mode which is enabled: (a) upon power-
2
8).
Dummy Clock Cycles
3
Figure 5-2 on page
8
Figure 5-3 on page
9
8). Data changes during SCL high
Start bit
8).
8700D–SEEPR–8/10
Stop bit