24C02CT/SN Microchip Technology, 24C02CT/SN Datasheet - Page 9

• Manufacturer Part Number: 24C02CT/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24C02CT/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0
6.1
Following the Start signal from the master, the device
code (4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24C02C.
After receiving another Acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not gener-
ate Acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
6.2
The write control byte, word address and the first data
byte are transmitted to the 24C02C in the same way as
in a byte write. But instead of generating a Stop
condition, the master transmits up to 15 additional data
bytes to the 24C02C which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a Stop
condition. After the receipt of each word, the four lower
order Address Pointer bits are internally incremented
by one. The higher order four bits of the word address
remains constant. If the master should transmit more
than 16 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten.
FIGURE 6-1:
FIGURE 6-2:
© 2008 Microchip Technology Inc.
SDA Line
Bus Activity
Master
Bus Activity
SDA Line
Bus Activity
Master
Bus Activity
WRITE OPERATIONS
Byte Write
Page Write
S
T
A
R
T
S
S
S
T
A
R
T
BYTE WRITE
PAGE WRITE
Control
Byte
Control
Byte
A
C
K
Address (n)
Word
A
C
K
A
C
K
Address
Word
Data n
As with the byte write operation, once the Stop
condition is received an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the
protected portion of the array when the hardware write
protection has been enabled, the device will acknowl-
edge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
6.3
The WP pin must be tied to V
the upper half of the array (080-0FF) will be write-
protected. If the WP pin is tied to V
operations to all address locations are allowed.
Note:
Write Protection
A
C
K
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
A
C
K
Data n +1
Data
A
C
K
CC
or V
24C02C
Data n + 15
SS
DS21202J-page 9
. If tied to V
SS
, then write
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P
CC
,