24LC024-I/SN Microchip Technology, 24LC024-I/SN Datasheet - Page 4

• Manufacturer Part Number: 24LC024-I/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC024-I/SN

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 10 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LC024-I/SNG; 24LC024-I/SNG

24AA024/24LC024/24AA025/24LC025
2.0
2.1
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either V
2.4
WP is the hardware write-protect pin. It must be tied to
V
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
2.5
The 24AA024/24LC024/24AA025/24LC025 employs a
V
nal erase/write logic if the V
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
DS21210G-page 4
CC
CC
or V
threshold detector circuit which disables the inter-
PIN DESCRIPTIONS
SDA Serial Data
SCL Serial Clock
A0, A1, A2
WP (24XX024 Only)
SS
Noise Protection
. If tied to Vcc, hardware write protection is
CC
(typical 10 k
CC
CC
for 100 kHz, 2 k
or V
is below 1.5 volts at
SS
.
for
3.0
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
FUNCTIONAL DESCRIPTION
 2004 Microchip Technology Inc.