24AA024-I/ST Microchip Technology, 24AA024-I/ST Datasheet - Page 6

• Manufacturer Part Number: 24AA024-I/ST
• Description: IC EEPROM 2KBIT 400KHZ 8TSSOP
• Manufacturer: Microchip Technology

Specifications of 24AA024-I/ST

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24AA024I/ST

24AA024/24LC024/24AA025/24LC025
4.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Both data and clock lines remain high.
4.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
FIGURE 4-2:
DS21210N-page 6
SDA
SCL
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
SCL
SDA
(A)
BUS CHARACTERISTICS
Bus Not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
Data Valid (D)
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
Condition
Start
(B)
1
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
ACKNOWLEDGE TIMING
2
Data from transmitter
3
4
Acknowledge
Address or
Valid
5
(C)
6
to Change
7
Allowed
Data
Acknowledge
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.5
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
8
Note:
Bit
9
Acknowledge
The 24AA024/24LC024/24AA025/24LC025
does not generate any Acknowledge bits if
an internal programming cycle is in prog-
ress.
Data from transmitter
(D)
1
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
2
© 2009 Microchip Technology Inc.
3
Condition
Stop
(C)
(A)