24LCS52T-I/SN Microchip Technology, 24LCS52T-I/SN Datasheet - Page 6

• Manufacturer Part Number: 24LCS52T-I/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LCS52T-I/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24AA52/24LCS52
3.6
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 24XXX52 devices on the same bus and are used
to determine which device is accessed. The Chip
Select bits in the control byte must correspond to the
logic levels on the corresponding A2, A1 and A0 pins
for the device to respond. The device will not acknowl-
edge if you attempt a Read command with the control
code set to ‘0110’.
The eighth bit of slave address determines if the master
device wants to read or write to the 24XXX52
(Figure 3-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
FIGURE 3-2:
4.0
4.1
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 24XXX52.
DS21166J-page 6
Read
Write
Set Write-Protect
Register
Operation
Start
1
0
Device Addressing
WRITE OPERATIONS
Byte Write
0
1
Slave Address
1
1
Control
CONTROL BYTE
ALLOCATION
OR
Code
1010
1010
0110
0
0
A2
A2
Read/Write
A2 A1 A0
A2 A1 A0
A2 A1 A0
Select
A1
A1
Chip
A0
A0
R/W A
R/W
1
0
0
After receiving another Acknowledge signal from the
24XXX52, the master device will transmit the data word
to be written into the addressed memory location. The
24XXX52 acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle, which means that during this time, the 24XXX52
will not generate Acknowledge signals (Figure 4-1). If
an attempt is made to write to the array when the soft-
ware or hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if the write protection is enabled.
4.2
The write control byte, word address and the first data
byte are transmitted to the 24XXX52 in the same way
as in a byte write. Instead of generating a Stop condi-
tion, the master transmits up to 15 additional data bytes
to the 24XXX52, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
is made to write to the array when the hardware write
protection has been enabled, the device will acknowl-
edge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
Note:
Page Write
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer mul-
tiples of [page size – 1]. If a Page Write
command attempts to write across a phys-
ical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
© 2005 Microchip Technology Inc.