24LC21T/SN Microchip Technology, 24LC21T/SN Datasheet - Page 5

• Manufacturer Part Number: 24LC21T/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC21T/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the V
that a logic high level is required to enable write capa-
bility. This mode supports a two wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the Start and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
FIGURE 3-1:
FIGURE 3-2:
 2004 Microchip Technology Inc.
SCL
SDA
V
CLK
SDA
BIDIRECTIONAL MODE
SCL
(A)
CLK
input is disregarded, with the exception
Condition
Start
(B)
MODE TRANSITION
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Transmit-only mode
Acknowledge
Address or
T
Valid
(D)
VHZ
to Change
Bidirectional mode
Allowed
Data
3.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
Both data and clock lines remain high.
3.1.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Bidirectional Mode Bus
Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
(D)
24LC21
DS21095J-page 5
Condition
Stop
(C)
(A)