25LC020A-I/P Microchip Technology, 25LC020A-I/P Datasheet - Page 10

• Manufacturer Part Number: 25LC020A-I/P
• Description: IC EEPROM 2KBIT 10MHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 25LC020A-I/P

• Memory Size: 2K (256 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Memory Configuration: 256 X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25AA020A/25LC020A
2.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX020A is busy with a write operation. When set to
a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS21833D-page 10
W/R = writable/readable. R = read-only.
SCK
1
CS
SO
’, a write is in progress, when set to a ‘
X
7
–
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
5
–
X
0
STATUS REGISTER
X
4
–
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
W/R
BP1
High-Impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
Preliminary
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS register
10
5
11
4
© 2007 Microchip Technology Inc.
12
3
13
2
14
1
15
0