25LC080A-I/SN Microchip Technology, 25LC080A-I/SN Datasheet - Page 10

• Manufacturer Part Number: 25LC080A-I/SN
• Description: IC EEPROM 8KBIT 10MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC080A-I/SN

• Memory Size: 8K (1K x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 1 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 50 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25XX080A/B
2.5
The Read Status Register instruction (RDSR) provides
access to the Status Register. The Status Register may
be read at any time, even during a write cycle. The
Status Register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX080A/B is busy with a write operation. When set
to a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS21808D-page 10
W/R = writable/readable. R = read-only.
WPEN
SCK
W/R
CS
SO
7
1
SI
’, a write is in progress, when set to a ‘
Read Status Register Instruction
(RDSR)
6
–
X
0
5
–
X
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
4
–
X
0
1
W/R
BP1
high-impedance
3
0
instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read only. When set to
a ‘
Register, when set to a ‘
the array or the Status Register. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
Register. These commands are shown in Figure 2-4
and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is in Figure 2-7. These bits are nonvolatile and are
shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
8
1
’, the latch allows writes to the array or the Status
6
9
data from Status Register
10
5
11
4
© 2007 Microchip Technology Inc.
12
3
0
’, the latch prohibits writes to
13
2
14
1
15
0