AT26DF081A-SU Atmel, AT26DF081A-SU Datasheet - Page 14

• Manufacturer Part Number: AT26DF081A-SU
• Description: IC FLASH 8MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT26DF081A-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT26DF081-SU; AT26DF081-SU

8.4
14
Chip Erase
AT26DF081A
Figure 8-5.
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,
the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of t
The complete opcode must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no
erase will be performed. In addition, if any sector of the memory array is in the protected state,
then the Chip Erase command will not be executed, and the device will return to the idle state
once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to
the logical “0” state if a sector is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the t
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-
tion fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the
Status Register.
SCK
CS
SO
SI
Block Erase
MSB
HIGH-IMPEDANCE
C
0
C
1
C
2
OPCODE
C
3
C
4
CHPE
CHPE
C
5
C
.
6
time to determine if the device has finished erasing. At
C
7
MSB
A
8
A
9
A
10 11
A
ADDRESS BITS A23-A0
A
12
A
A
26
A
27 28
A
A
29 30
A
A
31
3600G–DFLASH–06/09