ATSAMA5D33-EK Atmel, ATSAMA5D33-EK Datasheet - Page 44

• Manufacturer Part Number: ATSAMA5D33-EK
• Description: Development Boards & Kits - ARM EVAL KIT SAMA5D33 CRYPTO
• Manufacturer: Atmel
• Series: SAMA5D4r

Specifications of ATSAMA5D33-EK

• Product: Evaluation Kits
• Tool Is For Evaluation Of: SAMA5D33
• Core: ARM
• Interface Type: Serial, USB
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 bit
• Description/function: Allows users to extensively evaluate, prototype and create application-specific designs
• Dimensions: 165 mm x 135 mm x 20 mm
• Maximum Operating Temperature: + 60 C
• Minimum Operating Temperature: 0 C
• For Use With: SAMA5D33

U3-H
SAMA5D3x
DDR_DQSN0
DDR_DQSN2
DDR_DQSN3
DDR_DQSN1
DDR_DQM0
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS2
DDR_DQS3
DDR_CLKN
DDR_CALN
DDR_CALP
DDR_VREF
DDR_DQM1
DDR_DQS1
DDR_D20
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_CLK
DDR_CKE
DDR_RAS
DDR_CAS
DDR_BA0
DDR_BA2
DDR_A10
DDR_A12
DDR_A13
DDR_D10
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D21
DDR_D31
DDR_BA1
DDR_A0
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A11
DDR_D0
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D11
DDR_CS
DDR_WE
DDR_A1
DDR_D1
100n/10V
B10
E10
D10
C10
H12
H17
H13
G17
G16
H15
F17
G15
F16
E17
G14
E16
D17
C18
D16
C17
B16
B18
C15
A18
C16
C14
D15
B14
A15
A14
E12
F12
A10
G12
E15
B15
D12
E18
G18
B17
B13
D18
F18
A17
A13
B12
A12
C12
E13
C13
C11
A9
D11
B9
A8
B8
F11
A7
D9
A6
A11
B11
E11
C8
B7
G11
A5
B5
E9
B6
F9
1
1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
C63
GND
DDR_RAS#
DDR_CAS#
DDR_CKE
DDR_WE#
DDR_BA0
DDR_BA1
DDR_BA2
DDR_DQS2
DDR_DQS3
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_VREF
DDR_VREF
group 1AB
TP13
TP12
DDR_ADDR
DDR_A[0-13]
5
5
5
5
5
5
5
DDR_CS#
DDR_DATA
DDR_D[0-31]
5
5
5
5
5
5
5
5
5
5
VDDIODDR
5
VDDIODDR
GND
GND
R50
R51
top/bot
top/bot
R10
200R
R13
200R
0402
0402
0R
0R
group 1AB
5
DNP
DDR_CK#
DDR_CK
2
DDR_ADDR
DDR_A[0-13]
2
DDR_CKE
VDDIODDR
BLM15AG121SN1D
5
5
L7
5
5
5
5
5
5
5
5
5
Differential
100 ohms
4u7/6V3/X5R
group 1AB
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
DDR_CK
DDR_CK#
C64
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
R11
1R
GND
group 3AB
GND
GND
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
L3
K3
L7
K7
L8
K9
K2
J8
K8
A3
E3
J3
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
L1
N1
U4
MT47H128M16RT-3:C
R12
1k5/1%
R14
1k5/1%
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU(A13)
RFU
RFU
BA0
BA1
BA2
WE#
CAS#
RAS#
CS#
ODT
CKE
CK
CK#
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
L3 & L8
GND
A
C62
100n/10V
C65
100n/10V
LDQS#/NU
UDQS#/NU
LDQS
UDQS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VREF
3
DQ10
DQ12
DQ13
DQ14
DQ15
3
DQ0
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ11
LDM
UDM
VDD
VDD
VDD
VDD
VDD
DQ1
NC
NC
Zo=50 ohms
G8
G2
H7
H3
H9
F9
C8
C2
D7
D3
D9
B9
F7
E8
B7
A8
F3
B3
A2
E2
J9
M9
A9
C3
C7
C9
E9
G3
G7
G9
J2
H1
F1
D1
B1
A1
E1
R1
C1
G1
J1
top/bot
GND
R72
R73
C44
C45
C48
C49
C52
C53
C56
C57
DDR_VREF
group 1AB
C60
100n/10V
group 1AB
DDR_D[0-15]
DDR_DQM0
DDR_DQM1
DDR_DATA
DDR_DQS0
DDR_DQS1
minimizing crosstalk with [DQ, DQS, DQM]
DDR_VREF
0402
0402
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
4k7
4k7
C109
C110
C108
C77
C79
C76
C111 100n/10V
C112 100n/10V
VDDIODDR
5
5
5
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
5
5
5
group 2A
GND
L3 & L8
GND
VDDIODDR
FILE
SIZE
PROJECT TITLE
SHEET TITLE
A4
GND
SAMA5D3x-CM v2.0f.scm
REV
R52
R53
Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA.
The layout EBI DDR2 should use controlled impedance traces of ZO = 50Ohm characteristic impedance.
Trace width = 0.13mm: target 50Ohm impedance.
Trace space = 0.30 to 0.38 mm.
4
4
0402
0402
DATE
20.9.2012
0R
0R
SAMA5D3x-CM
DDR2 INTERFACE
5
DNP
DDR_CKE
DDR_ADDR
DDR_A[0-13]
DESCRIPTION FILE
5
5
5
5
5
5
5
5
5
group 1AB
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
DDR_CK
DDR_CK#
GND
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
L3
K3
L7
K7
L8
K9
K2
J8
K8
A3
E3
J3
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
L1
N1
U5
MT47H128M16RT-3:C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU(A13)
RFU
RFU
BA0
BA1
BA2
WE#
CAS#
RAS#
CS#
ODT
CKE
CK
CK#
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
SHEET NO
DROWN
ISSUED
5
5
12.09.2012
Chenged U4 and U5
From MT47H64M16HR-25H to MT47H128M16RT-3:C
B
LDQS#/NU
UDQS#/NU
5
OF
LDQS
UDQS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VREF
DQ10
DQ12
DQ13
DQ14
DQ15
DQ0
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ11
LDM
UDM
VDD
VDD
VDD
VDD
VDD
DQ1
9
NC
NC
G8
G2
H7
H3
H9
F9
C8
C2
D7
D3
D9
B9
F7
E8
B7
A8
F3
B3
A2
E2
J9
M9
A9
C3
C7
C9
E9
G3
G7
G9
J2
H1
F1
D1
B1
A1
E1
R1
C1
G1
J1
GND
VDDIODDR
R70
R71
C46
C47
C50
C51
C54
C55
C58
C59
DDR_VREF
group 1AB
C61
100n/10V
DDR_DATA
DDR_D[16-31]
development tool
www.ronetix.at
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
0402
0402
DDR_DQS2
DDR_DQS3
DDR_DQM2
DDR_DQM3
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
4k7
4k7
C117
C118
C116
C114 100n/10V
C115 100n/10V
C113 100n/10V
C119 100n/10V
C120 100n/10V
5
100n/10V
100n/10V
100n/10V
5
5
5
5
group 2B
GND
L3 & L8
GND
6
6