MIKROE-453 mikroElektronika, MIKROE-453 Datasheet - Page 26

• Manufacturer Part Number: MIKROE-453
• Description: Development Boards & Kits - PIC/DSPIC LV18F V6 DEVELOPMENT SYSTEM
• Manufacturer: mikroElektronika

Specifications of MIKROE-453

• Rohs: yes
• Product: Development Kits
• Core: PIC
• Interface Type: ICD, IDC10, JTAG, RS-232, USB
• Operating Supply Voltage: 5 V, 9 V to 32 V
• Data Bus Width: 8 bit
• Description/function: Development Board Only, Touch Screen, Pencil, DS1820, LCD, Serial Cable, GLCD not included
• Dimensions: 265 mm x 220 mm
• For Use With: PIC

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MikroElektronika
Pull-up/pull-down resistors enable you to set the logic level on all microcontroller’s input pins when they are in idle state. Such level
depends on the position of the pull-up/pull-down jumper. The RG0 pin with the relevant DIP switch SW7, jumper J7 and RG0 push
button with jumper J12 are used here for the purpose of explaining the performance of pull-up/pull-down resistors. The principle of
their operation is the same as for all other microcontroller pins.
Figure 21-5: Jumper J7 in pull-down position and jumper J12 in pull-up position
Figure 21-6: Jumper J7 in pull-up and jumper J12 in pull-down position
Figure 21-7: Jumpers J7 and J12 in the same position
In case that jumpers J7 and J12 have the same
logic state, pressure on any button will not cause
input pins to change their logic state.
In order to enable the PORTG port pins to be
connected to pull-down resistors, it is necessary
to place jumper J7 in the Down position fi rst.
This enables any PORTG port pin to be supplied
with a logic zero (0V) in idle state over jumper
J7 and 8x10k resistor network. To provide the
RB0 pin with such signal, it is necessary to set
the RG0 switch on the DIP switch SW7 to the
ON position.
As a result, every time you press the RG0 push
button, a logic one (VCC voltage) will appear on
the RG0 pin, provided that jumper J12 is placed
in the VCC position.
In order to enable port PORTG pins to be
connected to pull-up resistors and the port input
pins to be supplied with a logic zero (0), it is
necessary to place jumper J7 in the Up position
and jumper J12 in the GND position. This
enables any port PORTG input pin to be driven
high (5V) in idle state over the 10k resistor.
As a result, every time you press the RG0 push
button, a logic zero (0V) will appear on the RG0
pin, provided that the RG0 switch is set to the
ON position.
LV 18F v6 Development System
LV 18F v6 Development System