S-93C66BR0I-J8T1G Seiko Instruments, S-93C66BR0I-J8T1G Datasheet - Page 11

• Manufacturer Part Number: S-93C66BR0I-J8T1G
• Description: IC EEPROM 4KBIT 500KHZ 8SOP
• Manufacturer: Seiko Instruments

Specifications of S-93C66BR0I-J8T1G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (256 x 16)
• Speed: 500kHz
• Interface: 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev.7.0
Operation
Start Bit
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start
bit is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
2. Start bit input failure
Instruction input finishes when CS goes low. A low level must be input to CS between commands during t
While a low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI inputs are
invalid and no instructions are allowed.
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks
can be adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit dummy clock for the S-
93C56B/66B.
• When the output status of the DO pin is high during the verify period after a write operation, if a high level is
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the
_00
input to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit has been input.
To prevent this failure, input a low level to the DI pin during the verify operation period (refer to “ 4.1 Verify
operation ”).
data output from the CPU and the serial memory collide may be generated, preventing successful input of the
start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO) ”.
Seiko Instruments Inc.
3-WIRE SERIAL E
S-93C46B/56B/66B
2
PROM
CDS
11
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