AC530 Fastrax, AC530 Datasheet - Page 24

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AC530

Manufacturer Part Number
AC530
Description
GPS Development Tools Application Board for UC530
Manufacturer
Fastrax
Datasheet

Specifications of AC530

Rohs
yes
Product
Application Boards
Tool Is For Evaluation Of
UC530
Frequency
1.575 GHz
Operating Supply Voltage
3.3 V
Interface Type
UART
Description/function
Fastrax Application Board AC530 provides the UC530 connectivity to the Fastrax Evaluation Kit or to other evaluation purposes
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Current
25 mA

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Manufacturer
Quantity
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Page 24 of 39
7 Reference design
The idea of the reference design is to give a guideline for the applications using the OEM GPS module. In itself it is
not a finished product, but an example that performs correctly.
In the following two chapters the reader is exposed to design rules that he should follow, when designing the GPS
receiver in to the application. By following the rules one end up having an optimal design with no unexpected
behavior caused by the PCB layout itself. In fact these guidelines are quite general in nature, and can be utilized in
any PCB design related to RF techniques or to high speed logic.
7.1
The following picture describes a minimum connectivity for a typical autonomous navigation application. It
consists of the UC530 module, which is powered by the main VDD supply (+3.3 V typ.) and backup supply VDD_B
(+3.0V typ) powered by battery BT1. The external by-pass capacitor C1 and C2 is used to de-couple the supply
inputs placed close to the pin.
Suggestion is to keep the backup supply VDD_B active all the time and host may use the VDD supply to control
module activity between Full Power and Backup operation modes. When needed the VDD can be connected
directly to a LiPo battery but in this case the backup battery BT1 must be charged from a separate 3V supply.
Embedded Antenna Signal (ANT) must be routed to RF-input (RF_IN) via a short trace between pads 16 and 17.
The host port is configured to UART by keeping GPIO 9 & 10 floating. Serial port TX output is connected to host
UART input. RX input connection to host UART output is required when sending commands to UC530. UART
signals are decoupled with series resistors R1 and R2 in order to minimize risk for internal EMI.
For optional Backup/Periodic modes of operation the external power switch U1 shall be assembled while omitting
by-pass resistor R9 (0R). The U1 power switch shall be controlled autonomously by the TIMER signal from UC530.
After the UC530 has been controlled to Autonomous Backup Mode or to Periodic Mode via an NMEA message, the
module can control VDD activity autonomously via TIMER signal that has control on the VDD power switch U1.
Host can wake up the module by toggling the GPS_ON control signal to high state (e.g. pulse > 0.5 s), which
enables the power switch U1 by via diode D2. Resistor R7 (0 ohm) adds an option for future upgrade with
FORCE_ON signal in case external power switch can be omitted.
Optional connectivity to host includes PPS, UI_FIX, 32K/DR_INT signals. UART Port 1 RX1 signal can be used
optionally as input for RTCM differential GPS messages.
Note that all I/O signal levels are CMOS 2.8V compatible (excluding TIMER and 32K/DR_INT signals that have 1.2 V
CMOS domain) and inputs are 3.6 V tolerable.
Some I/O signals have series resistors 47… 220 ohm, which are intended for RF-decoupling purposes to improve
rejection to internally generated EMI that may leak to embedded GPS antenna.
2012-05-03
UC530_Datasheet
Vibration Test
Shock Test
Reference circuit diagram
10G, 10… 1,000Hz, 1 Octave/min (amplitude 1.0mm max @
<70Hz)
100G pulse, duration 2ms, 5 Shock 2 directions 3 Axis = 30
Shocks
JESD22B103
JESD22B110

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