M25PE40-VMW6G NUMONYX, M25PE40-VMW6G Datasheet - Page 35

• Manufacturer Part Number: M25PE40-VMW6G
• Description: IC FLASH 4MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE40-VMW6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Memory Configuration: 512K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25PE40
6.11
Note:
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction is decoded only in the M25PE40 in the T9HX
process (see
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the targeted
sector and one data byte on Serial Data input (D). The instruction sequence is shown in
Figure
latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than t
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Write to Lock Register (WRLR) instruction sequence
Table 10.
1. The table rows in gray are true for products processed in the T7X process only (see
All sectors
S
C
D
page
17. Chip Select (S) must be driven High after the eighth bit of the data byte has been
6).
0
Sector
Lock Register in
Important note on page
1
2
Instruction
3
4
5
6
(1)
b7-b2
7
Bit
b1
b0
MSB
23
8
22 21
9 10
Sector Lock Down bit value
Sector Write Lock bit value
24-bit address
6).
3
28 29 30 31 32 33 34 35
2
1
0
MSB
7
6
SHSL
Value
Lock Register
5
‘0’
minimum value.
value
4
3
36 37 38
Important note on
2
1
0
39
Instructions
AI10784b
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