M45PE20-VMP6G NUMONYX, M45PE20-VMP6G Datasheet - Page 21

• Manufacturer Part Number: M45PE20-VMP6G
• Description: IC FLASH 2MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE20-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Memory Configuration: 256K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 25MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE20
6.4
6.4.1
6.4.2
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write cycle is in progress.
When one of these cycles is in progress, it is recommended to check the write in progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the status
register continuously, as shown in
The status bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write, program
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write, program or erase instruction is accepted.
Table 5.
1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is
Figure 9.
S
C
D
Q
automatically set and reset by the internal logic of the device).
b7
0
Status register format
Read status register (RDSR) instruction sequence and data-out sequence
0
High Impedance
1
0
2
Instruction
3
4
5
0
6
7
Figure
MSB
7
8
6
9 10 11 12 13 14 15
Status register out
0
5
9.
4
3
2
0
1
0
MSB
7
6
0
Status register out
5
4
3
WEL
2
(1)
1
Instructions
0
7
AI02031E
WIP
b0
(1)
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