M45PE80-VMP6TG NUMONYX, M45PE80-VMP6TG Datasheet - Page 13

• Manufacturer Part Number: M45PE80-VMP6TG
• Description: IC FLASH 8MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 12ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 4mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMP6TG; M45PE80-VMP6TGTR

4.3
4.4
4.5
4.6
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data up to 256
contiguous bytes at a time, provided that it involves only resetting bits to 0 that had
previously been set to 1. The following are times this use case might occur:
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
Table 13: AC characteristics (50 MHz
operation)).
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
Reset
An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the Power-on process, and only
driving it High when V
Active Power, Stand-by Power and Deep Power-Down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S) is High, the device is disabled, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Stand-by Power mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down Mode (DP) instruction) is executed. The device consumption drops further to
I
Deep Power-down Mode) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
CC2
. The device remains in this mode until another specific instruction (the Release from
The designer is programming the device for the first time;
The designer knows that the page has already been erased by an earlier Page Erase
(PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast
stream of data, having first performed the erase cycle when time was available;
The designer knows that the change involves only resetting bits to 0 that are still set to
1. When this method is possible, it has the additional advantage of minimizing the
number of unnecessary erase operations, and the extra stress incurred by each page.
Deep Power-down
CC
PW
has reached the correct voltage level, V
, t
PP
, t
PE
, or t
(DP)). This can be used as an extra software protection
operation), and
SE
). The Write In Progress (WIP) bit is provided in the
Table 14.: AC characteristics (75 MHz
CC
CC1
(min).
Page Program
.
(PP),
13/48