M25P64-VME6TG NUMONYX, M25P64-VME6TG Datasheet
M25P64-VME6TG
Specifications of M25P64-VME6TG
M25P64-VME6TGTR
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M25P64-VME6TG Summary of contents
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... More than 100 000 Erase/Program cycles per sector More than 20-year data retention Packages – RoHS compliant Automotive certified parts available March 2010 64 Mbit, low voltage, Serial Flash memory with 75 MHz SPI bus interface = Rev 12 M25P64 VDFPN8 (ME) 8 × (MLP8) SO16 (MF) 300 mils width 1/55 www.numonyx.com 1 ...
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... Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR ...
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WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8. Power-Up timing and VWI threshold Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 11 ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10 ...
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... Description The M25P64 Mbit ( Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus instructions allowing clock frequency MHz. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment ...
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... CC V Ground SS Figure 2. VDFPN connections 1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical M25P64 V SS AI07485B Function M25P64 HOLD W ...
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... Figure 3. SO connections Don’t Use 2. See Section 11: Package mechanical 8/55 M25P64 HOLD W/V PP AI07486C for package dimensions, and how to identify pin-1. ...
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Signal description 2.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) This input ...
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... If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA ...
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... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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Active Power and Standby Power modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P64 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertant changes while the power supply is outside the operating specification. ...
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Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is ...
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... Memory organization The memory is organized as: 8388608 bytes (8 bits each) 128 sectors (512 Kbits, 65536 bytes each) 32768 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Table 3. Memory organization Sector 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 18/55 Address range 7F0000h 7E0000h 7D0000h 7C0000h 7B0000h 7A0000h ...
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... Table 3. Memory organization (continued) Sector Address range 5C0000h 5B0000h 5A0000h 590000h 580000h 570000h 560000h 550000h 540000h 530000h 520000h 510000h 500000h 4F0000h 4E0000h 4D0000h 4C0000h 4B0000h 4A0000h 490000h 480000h 470000h 460000h 450000h 440000h 430000h 420000h 410000h 400000h 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h ...
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... Table 3. Memory organization (continued) Sector 20/55 Address range 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h ...
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... Table 3. Memory organization (continued) Sector Address range 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh ...
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... That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected ...
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Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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... Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h). ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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... Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set ...
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... BP2, BP1 and BP0 bits can be changed Status Register is Hardware write protected e The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed ) is W Memory content (1) Protected area Unprotected area Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Figure 15. Page Program (PP) instruction sequence Instruction Data Byte ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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... Figure 18. Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h. 36/55 Figure 18 Dummy Bytes ...
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Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 19. Power-up timing (max (min) Reset State of the Device V WI Table 8. Power-Up timing and VWI threshold Symbol ( (min low VSL CC (1) t Time delay ...
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... These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Figure 20. AC measurement I/O waveform Table 13. Capacitance Symbol Parameter C Output Capacitance (Q) OUT C Input Capacitance (other pins Sampled only, not 100% tested Table 14. DC characteristics Symbol Parameter I Input Leakage Current ...
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Table 15. DC characteristics process technology T9HX Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating ...
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Table 16. AC characteristics Test conditions specified in Symbol Alt. Clock Frequency for the following instructions: FAST_READ PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR f Clock Frequency for READ instructions R ( ...
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Table 17. AC characteristics, T9HX parts (page Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, SE, BE, WREN, WRDI, RDID RDSR, WRSR Clock frequency for read ...
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Table 17. AC characteristics, T9HX parts (page Test conditions specified in Symbol Alt. t Sector erase cycle time SE t Bulk erase cycle time BE 1. Technology T9HX devices are identified by process identification digit "4" in ...
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Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1 W/V PP tWHSL High Impedance Q Figure 23. Hold timing HOLD 46/55 tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439b ...
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Figure 24. Output timing S C tCLQV tCLQX tCLQX Q ADDR D LSB IN Figure 25. V timing PPH PP, SE PPH W/V PP tVPPHSL tCH tCLQV tCL tQLQH tQHQL End of PP ...
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Package mechanical Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package ...
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Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width SO-H 1. Drawing is not to scale. Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width, ...
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... The lithography digit is present only in the automotive parts ordering scheme. 5. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive envirnoment. The High Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest Numonyx sales office for a copy. 50/55 M25P64 – (1) ...
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... For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Tested Parts from the non Auto Tested parts). Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. 52/55 M25P64 – ...
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... Figure 4: Bus master and memory devices on the SPI bus 5 I maximum value updated in CC1 Hardware Write Protection feature added to VCC supply voltage and VSS ground Figure 4: Bus master and memory devices on the SPI bus explanatory paragraph added Power-up The Write In Progress (WIP) bit is V max modified and T IO LEAD ratings ...
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... Applied Numonyx branding. To provide support for the Automotive market, added the following: – Automotive bullet to cover page; 8 – Grade 3 and grade 6 information to – Table 11.: Data Retention and Endurance – Automotive information to Added a lithography note to 9 Added information supporting 75 MHz. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...