M25PX64-VZM6TP NUMONYX, M25PX64-VZM6TP Datasheet - Page 53

• Manufacturer Part Number: M25PX64-VZM6TP
• Description: IC FLASH 64MBIT 75MHZ 24TBGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX64-VZM6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX64-VZM6TPTR

7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold voltage, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page program (PP), dual input fast
program (DIFP), program OTP (POTP), subsector erase (SSE), sector erase (SE), bulk
erase (BE), write status register (WRSR) and write to lock register (WRLR) instructions until
a time delay of t
However, the correct operation of the device is not guaranteed if, by this time, V
below V
the later of:
These values are specified in
If the time, t
for read instructions even if the t
After power-up, the device is in the following state:
Normal precautions must be taken for supply line decoupling, to stabilize the V
Each device in a system should have the V
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction (the designer needs to be aware that if power-down occurs while a write,
program or erase cycle is in progress, some data corruption may result).
V
V
t
t
The device is in the standby power mode (not the deep power-down mode)
The write enable latch (WEL) bit is reset
The write in progress (WIP) bit is reset
The lock registers are configured as: (write lock bit, lock down bit) = (0,0).
V
voltage range.
PUW
VSL
CC
SS
PPH
CC
(min) at power-up, and then for a further delay of t
at power-down.
after V
after V
(min). No write status register, program or erase instructions should be sent until
must be applied only when V
VSL
, has elapsed, after V
PUW
CC
CC
has passed the V
has passed the V
has elapsed after the moment that V
CC
WI
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table
CC
PUW
) until V
Section 3: SPI
11.
CC
CC
delay has not yet fully elapsed.
WI
(min) level.
CC
rises above V
threshold
CC
WI
is stable and in the V
CC
reaches the correct value:
– all operations are disabled, and the device
line decoupled by a suitable capacitor close
modes.
CC
(min), the device can be selected
CC
VSL
rises above the V
CC
(min) to V
CC
is less than the
CC
WI
CC
(max)
CC
threshold.
supply.
is still
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