N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 81

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
Table 21.
1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
9.1.25
DQ0
1
0
1
0
DQ1
W / VPP
Signal
C
Status register
S
0
0
1
1
SRWD
bit
Protection modes
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 33. Read Lock Register instruction and data-out sequence
0
format.
1
High Impedance
Software
protected
(SPM2)
Hardware
protected
(HPM)
Mode
2
Instruction
3
4
Status register is writeable, if the
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP3,
BP2, BP1, and BP0 bits can be
changed.
Status Register is hardware write
protected. The values in the
SRWD, TB, BP3, BP2, BP1 and
BP0 bits cannot be changed
5
Write protection of the status
6
7
MSB
23
8
register
22 21
9 10
24-bit address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31 32 33 34 35
2
1
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
0
Protected area
MSB
7
6
Lock register out
5
Memory content
©2010 Micron Technology, Inc. All rights reserved.
4
(1)
3
36 37 38
2
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
Unprotected area
1
0
39
Instructions
Table 2:
81/157
(1)